1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2019 David Lechner <david@lechnology.com>
4 *
5 * Counter driver for Texas Instruments Enhanced Quadrature Encoder Pulse (eQEP)
6 */
7
8 #include <linux/bitops.h>
9 #include <linux/clk.h>
10 #include <linux/counter.h>
11 #include <linux/kernel.h>
12 #include <linux/mod_devicetable.h>
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/regmap.h>
17 #include <linux/types.h>
18
19 /* 32-bit registers */
20 #define QPOSCNT 0x0
21 #define QPOSINIT 0x4
22 #define QPOSMAX 0x8
23 #define QPOSCMP 0xc
24 #define QPOSILAT 0x10
25 #define QPOSSLAT 0x14
26 #define QPOSLAT 0x18
27 #define QUTMR 0x1c
28 #define QUPRD 0x20
29
30 /* 16-bit registers */
31 #define QWDTMR 0x0 /* 0x24 */
32 #define QWDPRD 0x2 /* 0x26 */
33 #define QDECCTL 0x4 /* 0x28 */
34 #define QEPCTL 0x6 /* 0x2a */
35 #define QCAPCTL 0x8 /* 0x2c */
36 #define QPOSCTL 0xa /* 0x2e */
37 #define QEINT 0xc /* 0x30 */
38 #define QFLG 0xe /* 0x32 */
39 #define QCLR 0x10 /* 0x34 */
40 #define QFRC 0x12 /* 0x36 */
41 #define QEPSTS 0x14 /* 0x38 */
42 #define QCTMR 0x16 /* 0x3a */
43 #define QCPRD 0x18 /* 0x3c */
44 #define QCTMRLAT 0x1a /* 0x3e */
45 #define QCPRDLAT 0x1c /* 0x40 */
46
47 #define QDECCTL_QSRC_SHIFT 14
48 #define QDECCTL_QSRC GENMASK(15, 14)
49 #define QDECCTL_SOEN BIT(13)
50 #define QDECCTL_SPSEL BIT(12)
51 #define QDECCTL_XCR BIT(11)
52 #define QDECCTL_SWAP BIT(10)
53 #define QDECCTL_IGATE BIT(9)
54 #define QDECCTL_QAP BIT(8)
55 #define QDECCTL_QBP BIT(7)
56 #define QDECCTL_QIP BIT(6)
57 #define QDECCTL_QSP BIT(5)
58
59 #define QEPCTL_FREE_SOFT GENMASK(15, 14)
60 #define QEPCTL_PCRM GENMASK(13, 12)
61 #define QEPCTL_SEI GENMASK(11, 10)
62 #define QEPCTL_IEI GENMASK(9, 8)
63 #define QEPCTL_SWI BIT(7)
64 #define QEPCTL_SEL BIT(6)
65 #define QEPCTL_IEL GENMASK(5, 4)
66 #define QEPCTL_PHEN BIT(3)
67 #define QEPCTL_QCLM BIT(2)
68 #define QEPCTL_UTE BIT(1)
69 #define QEPCTL_WDE BIT(0)
70
71 /* EQEP Inputs */
72 enum {
73 TI_EQEP_SIGNAL_QEPA, /* QEPA/XCLK */
74 TI_EQEP_SIGNAL_QEPB, /* QEPB/XDIR */
75 };
76
77 /* Position Counter Input Modes */
78 enum ti_eqep_count_func {
79 TI_EQEP_COUNT_FUNC_QUAD_COUNT,
80 TI_EQEP_COUNT_FUNC_DIR_COUNT,
81 TI_EQEP_COUNT_FUNC_UP_COUNT,
82 TI_EQEP_COUNT_FUNC_DOWN_COUNT,
83 };
84
85 struct ti_eqep_cnt {
86 struct counter_device counter;
87 struct regmap *regmap32;
88 struct regmap *regmap16;
89 };
90
ti_eqep_count_from_counter(struct counter_device * counter)91 static struct ti_eqep_cnt *ti_eqep_count_from_counter(struct counter_device *counter)
92 {
93 return counter_priv(counter);
94 }
95
ti_eqep_count_read(struct counter_device * counter,struct counter_count * count,u64 * val)96 static int ti_eqep_count_read(struct counter_device *counter,
97 struct counter_count *count, u64 *val)
98 {
99 struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter);
100 u32 cnt;
101
102 regmap_read(priv->regmap32, QPOSCNT, &cnt);
103 *val = cnt;
104
105 return 0;
106 }
107
ti_eqep_count_write(struct counter_device * counter,struct counter_count * count,u64 val)108 static int ti_eqep_count_write(struct counter_device *counter,
109 struct counter_count *count, u64 val)
110 {
111 struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter);
112 u32 max;
113
114 regmap_read(priv->regmap32, QPOSMAX, &max);
115 if (val > max)
116 return -EINVAL;
117
118 return regmap_write(priv->regmap32, QPOSCNT, val);
119 }
120
ti_eqep_function_read(struct counter_device * counter,struct counter_count * count,enum counter_function * function)121 static int ti_eqep_function_read(struct counter_device *counter,
122 struct counter_count *count,
123 enum counter_function *function)
124 {
125 struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter);
126 u32 qdecctl;
127
128 regmap_read(priv->regmap16, QDECCTL, &qdecctl);
129
130 switch ((qdecctl & QDECCTL_QSRC) >> QDECCTL_QSRC_SHIFT) {
131 case TI_EQEP_COUNT_FUNC_QUAD_COUNT:
132 *function = COUNTER_FUNCTION_QUADRATURE_X4;
133 break;
134 case TI_EQEP_COUNT_FUNC_DIR_COUNT:
135 *function = COUNTER_FUNCTION_PULSE_DIRECTION;
136 break;
137 case TI_EQEP_COUNT_FUNC_UP_COUNT:
138 *function = COUNTER_FUNCTION_INCREASE;
139 break;
140 case TI_EQEP_COUNT_FUNC_DOWN_COUNT:
141 *function = COUNTER_FUNCTION_DECREASE;
142 break;
143 }
144
145 return 0;
146 }
147
ti_eqep_function_write(struct counter_device * counter,struct counter_count * count,enum counter_function function)148 static int ti_eqep_function_write(struct counter_device *counter,
149 struct counter_count *count,
150 enum counter_function function)
151 {
152 struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter);
153 enum ti_eqep_count_func qsrc;
154
155 switch (function) {
156 case COUNTER_FUNCTION_QUADRATURE_X4:
157 qsrc = TI_EQEP_COUNT_FUNC_QUAD_COUNT;
158 break;
159 case COUNTER_FUNCTION_PULSE_DIRECTION:
160 qsrc = TI_EQEP_COUNT_FUNC_DIR_COUNT;
161 break;
162 case COUNTER_FUNCTION_INCREASE:
163 qsrc = TI_EQEP_COUNT_FUNC_UP_COUNT;
164 break;
165 case COUNTER_FUNCTION_DECREASE:
166 qsrc = TI_EQEP_COUNT_FUNC_DOWN_COUNT;
167 break;
168 default:
169 /* should never reach this path */
170 return -EINVAL;
171 }
172
173 return regmap_write_bits(priv->regmap16, QDECCTL, QDECCTL_QSRC,
174 qsrc << QDECCTL_QSRC_SHIFT);
175 }
176
ti_eqep_action_read(struct counter_device * counter,struct counter_count * count,struct counter_synapse * synapse,enum counter_synapse_action * action)177 static int ti_eqep_action_read(struct counter_device *counter,
178 struct counter_count *count,
179 struct counter_synapse *synapse,
180 enum counter_synapse_action *action)
181 {
182 struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter);
183 enum counter_function function;
184 u32 qdecctl;
185 int err;
186
187 err = ti_eqep_function_read(counter, count, &function);
188 if (err)
189 return err;
190
191 switch (function) {
192 case COUNTER_FUNCTION_QUADRATURE_X4:
193 /* In quadrature mode, the rising and falling edge of both
194 * QEPA and QEPB trigger QCLK.
195 */
196 *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
197 return 0;
198 case COUNTER_FUNCTION_PULSE_DIRECTION:
199 /* In direction-count mode only rising edge of QEPA is counted
200 * and QEPB gives direction.
201 */
202 switch (synapse->signal->id) {
203 case TI_EQEP_SIGNAL_QEPA:
204 *action = COUNTER_SYNAPSE_ACTION_RISING_EDGE;
205 return 0;
206 case TI_EQEP_SIGNAL_QEPB:
207 *action = COUNTER_SYNAPSE_ACTION_NONE;
208 return 0;
209 default:
210 /* should never reach this path */
211 return -EINVAL;
212 }
213 case COUNTER_FUNCTION_INCREASE:
214 case COUNTER_FUNCTION_DECREASE:
215 /* In up/down-count modes only QEPA is counted and QEPB is not
216 * used.
217 */
218 switch (synapse->signal->id) {
219 case TI_EQEP_SIGNAL_QEPA:
220 err = regmap_read(priv->regmap16, QDECCTL, &qdecctl);
221 if (err)
222 return err;
223
224 if (qdecctl & QDECCTL_XCR)
225 *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
226 else
227 *action = COUNTER_SYNAPSE_ACTION_RISING_EDGE;
228 return 0;
229 case TI_EQEP_SIGNAL_QEPB:
230 *action = COUNTER_SYNAPSE_ACTION_NONE;
231 return 0;
232 default:
233 /* should never reach this path */
234 return -EINVAL;
235 }
236 default:
237 /* should never reach this path */
238 return -EINVAL;
239 }
240 }
241
242 static const struct counter_ops ti_eqep_counter_ops = {
243 .count_read = ti_eqep_count_read,
244 .count_write = ti_eqep_count_write,
245 .function_read = ti_eqep_function_read,
246 .function_write = ti_eqep_function_write,
247 .action_read = ti_eqep_action_read,
248 };
249
ti_eqep_position_ceiling_read(struct counter_device * counter,struct counter_count * count,u64 * ceiling)250 static int ti_eqep_position_ceiling_read(struct counter_device *counter,
251 struct counter_count *count,
252 u64 *ceiling)
253 {
254 struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter);
255 u32 qposmax;
256
257 regmap_read(priv->regmap32, QPOSMAX, &qposmax);
258
259 *ceiling = qposmax;
260
261 return 0;
262 }
263
ti_eqep_position_ceiling_write(struct counter_device * counter,struct counter_count * count,u64 ceiling)264 static int ti_eqep_position_ceiling_write(struct counter_device *counter,
265 struct counter_count *count,
266 u64 ceiling)
267 {
268 struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter);
269
270 if (ceiling != (u32)ceiling)
271 return -ERANGE;
272
273 regmap_write(priv->regmap32, QPOSMAX, ceiling);
274
275 return 0;
276 }
277
ti_eqep_position_enable_read(struct counter_device * counter,struct counter_count * count,u8 * enable)278 static int ti_eqep_position_enable_read(struct counter_device *counter,
279 struct counter_count *count, u8 *enable)
280 {
281 struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter);
282 u32 qepctl;
283
284 regmap_read(priv->regmap16, QEPCTL, &qepctl);
285
286 *enable = !!(qepctl & QEPCTL_PHEN);
287
288 return 0;
289 }
290
ti_eqep_position_enable_write(struct counter_device * counter,struct counter_count * count,u8 enable)291 static int ti_eqep_position_enable_write(struct counter_device *counter,
292 struct counter_count *count, u8 enable)
293 {
294 struct ti_eqep_cnt *priv = ti_eqep_count_from_counter(counter);
295
296 regmap_write_bits(priv->regmap16, QEPCTL, QEPCTL_PHEN, enable ? -1 : 0);
297
298 return 0;
299 }
300
301 static struct counter_comp ti_eqep_position_ext[] = {
302 COUNTER_COMP_CEILING(ti_eqep_position_ceiling_read,
303 ti_eqep_position_ceiling_write),
304 COUNTER_COMP_ENABLE(ti_eqep_position_enable_read,
305 ti_eqep_position_enable_write),
306 };
307
308 static struct counter_signal ti_eqep_signals[] = {
309 [TI_EQEP_SIGNAL_QEPA] = {
310 .id = TI_EQEP_SIGNAL_QEPA,
311 .name = "QEPA"
312 },
313 [TI_EQEP_SIGNAL_QEPB] = {
314 .id = TI_EQEP_SIGNAL_QEPB,
315 .name = "QEPB"
316 },
317 };
318
319 static const enum counter_function ti_eqep_position_functions[] = {
320 COUNTER_FUNCTION_QUADRATURE_X4,
321 COUNTER_FUNCTION_PULSE_DIRECTION,
322 COUNTER_FUNCTION_INCREASE,
323 COUNTER_FUNCTION_DECREASE,
324 };
325
326 static const enum counter_synapse_action ti_eqep_position_synapse_actions[] = {
327 COUNTER_SYNAPSE_ACTION_BOTH_EDGES,
328 COUNTER_SYNAPSE_ACTION_RISING_EDGE,
329 COUNTER_SYNAPSE_ACTION_NONE,
330 };
331
332 static struct counter_synapse ti_eqep_position_synapses[] = {
333 {
334 .actions_list = ti_eqep_position_synapse_actions,
335 .num_actions = ARRAY_SIZE(ti_eqep_position_synapse_actions),
336 .signal = &ti_eqep_signals[TI_EQEP_SIGNAL_QEPA],
337 },
338 {
339 .actions_list = ti_eqep_position_synapse_actions,
340 .num_actions = ARRAY_SIZE(ti_eqep_position_synapse_actions),
341 .signal = &ti_eqep_signals[TI_EQEP_SIGNAL_QEPB],
342 },
343 };
344
345 static struct counter_count ti_eqep_counts[] = {
346 {
347 .id = 0,
348 .name = "QPOSCNT",
349 .functions_list = ti_eqep_position_functions,
350 .num_functions = ARRAY_SIZE(ti_eqep_position_functions),
351 .synapses = ti_eqep_position_synapses,
352 .num_synapses = ARRAY_SIZE(ti_eqep_position_synapses),
353 .ext = ti_eqep_position_ext,
354 .num_ext = ARRAY_SIZE(ti_eqep_position_ext),
355 },
356 };
357
358 static const struct regmap_config ti_eqep_regmap32_config = {
359 .name = "32-bit",
360 .reg_bits = 32,
361 .val_bits = 32,
362 .reg_stride = 4,
363 .max_register = QUPRD,
364 };
365
366 static const struct regmap_config ti_eqep_regmap16_config = {
367 .name = "16-bit",
368 .reg_bits = 16,
369 .val_bits = 16,
370 .reg_stride = 2,
371 .max_register = QCPRDLAT,
372 };
373
ti_eqep_probe(struct platform_device * pdev)374 static int ti_eqep_probe(struct platform_device *pdev)
375 {
376 struct device *dev = &pdev->dev;
377 struct counter_device *counter;
378 struct ti_eqep_cnt *priv;
379 void __iomem *base;
380 struct clk *clk;
381 int err;
382
383 counter = devm_counter_alloc(dev, sizeof(*priv));
384 if (!counter)
385 return -ENOMEM;
386 priv = counter_priv(counter);
387
388 base = devm_platform_ioremap_resource(pdev, 0);
389 if (IS_ERR(base))
390 return PTR_ERR(base);
391
392 priv->regmap32 = devm_regmap_init_mmio(dev, base,
393 &ti_eqep_regmap32_config);
394 if (IS_ERR(priv->regmap32))
395 return PTR_ERR(priv->regmap32);
396
397 priv->regmap16 = devm_regmap_init_mmio(dev, base + 0x24,
398 &ti_eqep_regmap16_config);
399 if (IS_ERR(priv->regmap16))
400 return PTR_ERR(priv->regmap16);
401
402 counter->name = dev_name(dev);
403 counter->parent = dev;
404 counter->ops = &ti_eqep_counter_ops;
405 counter->counts = ti_eqep_counts;
406 counter->num_counts = ARRAY_SIZE(ti_eqep_counts);
407 counter->signals = ti_eqep_signals;
408 counter->num_signals = ARRAY_SIZE(ti_eqep_signals);
409
410 platform_set_drvdata(pdev, counter);
411
412 /*
413 * Need to make sure power is turned on. On AM33xx, this comes from the
414 * parent PWMSS bus driver. On AM17xx, this comes from the PSC power
415 * domain.
416 */
417 pm_runtime_enable(dev);
418 pm_runtime_get_sync(dev);
419
420 clk = devm_clk_get_enabled(dev, NULL);
421 if (IS_ERR(clk))
422 return dev_err_probe(dev, PTR_ERR(clk), "failed to enable clock\n");
423
424 err = counter_add(counter);
425 if (err < 0) {
426 pm_runtime_put_sync(dev);
427 pm_runtime_disable(dev);
428 return err;
429 }
430
431 return 0;
432 }
433
ti_eqep_remove(struct platform_device * pdev)434 static int ti_eqep_remove(struct platform_device *pdev)
435 {
436 struct counter_device *counter = platform_get_drvdata(pdev);
437 struct device *dev = &pdev->dev;
438
439 counter_unregister(counter);
440 pm_runtime_put_sync(dev);
441 pm_runtime_disable(dev);
442
443 return 0;
444 }
445
446 static const struct of_device_id ti_eqep_of_match[] = {
447 { .compatible = "ti,am3352-eqep", },
448 { },
449 };
450 MODULE_DEVICE_TABLE(of, ti_eqep_of_match);
451
452 static struct platform_driver ti_eqep_driver = {
453 .probe = ti_eqep_probe,
454 .remove = ti_eqep_remove,
455 .driver = {
456 .name = "ti-eqep-cnt",
457 .of_match_table = ti_eqep_of_match,
458 },
459 };
460 module_platform_driver(ti_eqep_driver);
461
462 MODULE_AUTHOR("David Lechner <david@lechnology.com>");
463 MODULE_DESCRIPTION("TI eQEP counter driver");
464 MODULE_LICENSE("GPL v2");
465 MODULE_IMPORT_NS(COUNTER);
466