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Searched refs:QCA956X_PLL_DDR_CONFIG_REG (Results 1 – 3 of 3) sorted by relevance

/openbmc/linux/arch/mips/ath79/
H A Dclock.c563 pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG_REG); in qca956x_clocks_init()
/openbmc/u-boot/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h519 #define QCA956X_PLL_DDR_CONFIG_REG 0x08 macro
/openbmc/linux/arch/mips/include/asm/mach-ath79/
H A Dar71xx_regs.h434 #define QCA956X_PLL_DDR_CONFIG_REG 0x08 macro