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Searched refs:QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/arch/mips/mach-ath79/qca953x/
H A Dclk.c82 & QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK) + 1; in get_clocks()
/openbmc/linux/arch/mips/ath79/
H A Dclock.c409 QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK; in qca953x_clocks_init()
/openbmc/u-boot/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h453 #define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f macro
/openbmc/linux/arch/mips/include/asm/mach-ath79/
H A Dar71xx_regs.h383 #define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f macro