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Searched refs:QCA953X_DDR_REG_CTL_CONF (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/mips/mach-ath79/qca953x/
H A Dddr.c228 writel(DDR_CTL_CONFIG_VAL, regs + QCA953X_DDR_REG_CTL_CONF); in ddr_init()
306 regs + QCA953X_DDR_REG_CTL_CONF); in ddr_init()
/openbmc/u-boot/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h278 #define QCA953X_DDR_REG_CTL_CONF 0x108 macro