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Searched refs:QCA953X_DDR_REG_CONFIG3 (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/mips/mach-ath79/qca953x/
H A Dddr.c250 writel(DDR1_CONF3_REG_VAL, regs + QCA953X_DDR_REG_CONFIG3); in ddr_init()
328 writel(DDR2_CONF3_REG_VAL, regs + QCA953X_DDR_REG_CONFIG3); in ddr_init()
/openbmc/u-boot/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h279 #define QCA953X_DDR_REG_CONFIG3 0x15c macro