Searched refs:Pixel (Results 1 – 25 of 79) sorted by relevance
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| /openbmc/linux/Documentation/devicetree/bindings/display/bridge/ |
| H A D | fsl,imx8qxp-pxl2dpi.yaml | 7 title: Freescale i.MX8qxp Pixel Link to Display Pixel Interface
13 The Freescale i.MX8qxp Pixel Link to Display Pixel Interface(PXL2DPI)
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| H A D | fsl,imx8qxp-pixel-link.yaml | 7 title: Freescale i.MX8qm/qxp Display Pixel Link
13 The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard
21 The i.MX8qm/qxp Display Pixel Link is accessed via System Controller Unit(SCU)
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| H A D | fsl,imx8qxp-pixel-combiner.yaml | 7 title: Freescale i.MX8qm/qxp Pixel Combiner
13 The Freescale i.MX8qm/qxp Pixel Combiner takes two output streams from a
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| /openbmc/u-boot/board/google/ |
| H A D | Kconfig | 14 This is the Chromebook Pixel released in 2013. It uses an Intel
26 This is the Chromebook Pixel released in 2013. With this config
46 This is the Chromebook Pixel released in 2015. It uses an Intel
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | qcom,gcc-msm8953.yaml | 28 - description: Pixel clock from DSI PHY0
30 - description: Pixel clock from DSI PHY1
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| H A D | qcom,gcc-msm8976.yaml | 29 - description: Pixel clock from DSI PHY0
31 - description: Pixel clock from DSI PHY1
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| H A D | qcom,dispcc-sm6125.yaml | 27 - description: Pixel clock from DSI PHY0
28 - description: Pixel clock from DSI PHY1
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| H A D | qcom,sdm845-dispcc.yaml | 31 - description: Pixel clock from DSI PHY0
33 - description: Pixel clock from DSI PHY1
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| H A D | qcom,dispcc-sm8x50.yaml | 33 - description: Pixel clock from DSI PHY0
35 - description: Pixel clock from DSI PHY1
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| H A D | qcom,sm8450-dispcc.yaml | 31 - description: Pixel clock from DSI PHY0
33 - description: Pixel clock from DSI PHY1
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| H A D | qcom,sm8550-dispcc.yaml | 31 - description: Pixel clock from DSI PHY0
33 - description: Pixel clock from DSI PHY1
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| H A D | qcom,sm6375-dispcc.yaml | 30 - description: Pixel clock from DSI PHY
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| H A D | qcom,sm6115-dispcc.yaml | 28 - description: Pixel clock from DSI PHY0
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| H A D | qcom,sc7180-dispcc.yaml | 27 - description: Pixel clock from DSI PHY
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| H A D | qcom,dispcc-sm6350.yaml | 27 - description: Pixel clock from DSI PHY
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| H A D | qcom,qcm2290-dispcc.yaml | 29 - description: Pixel clock from DSI PHY
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| /openbmc/linux/Documentation/devicetree/bindings/media/ |
| H A D | fsl,imx6ull-pxp.yaml | 8 title: Freescale Pixel Pipeline
15 The Pixel Pipeline (PXP) is a memory-to-memory graphics processing engine
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| H A D | nxp,imx8-isi.yaml | 15 sources. The inputs to the ISI go through Pixel Link interfaces, and their
59 Ports represent the Pixel Link inputs to the ISI. Their number and
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| /openbmc/linux/Documentation/devicetree/bindings/gpu/ |
| H A D | arm,mali-utgard.yaml | 73 - pp # Pixel Processor broadcast interrupt (mali-450 only)
74 - pp0 # Pixel Processor X interrupt (X from 0 to 7)
75 - ppmmu0 # Pixel Processor X MMU interrupt (X from 0 to 7)
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| /openbmc/linux/Documentation/devicetree/bindings/display/rockchip/ |
| H A D | rockchip-vop2.yaml | 48 - description: Pixel clock for video port 0.
49 - description: Pixel clock for video port 1.
50 - description: Pixel clock for video port 2.
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| /openbmc/linux/Documentation/gpu/amdgpu/display/ |
| H A D | dc-glossary.rst | 31 Bits Per Pixel
34 * PCLK: Pixel Clock
41 * PPLL: Pixel PLL
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| /openbmc/linux/drivers/video/fbdev/ |
| H A D | pxa3xx-regs.h | 91 #define LCCR1_DisWdth(Pixel) (((Pixel) - 1) << FShft (LCCR1_PPL)) argument
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| /openbmc/linux/drivers/media/platform/nxp/ |
| H A D | Kconfig | 47 tristate "NXP i.MX Pixel Pipeline (PXP)"
53 The i.MX Pixel Pipeline is a memory-to-memory engine for scaling,
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| /openbmc/u-boot/board/coreboot/ |
| H A D | Kconfig | 19 Pixel when launched.
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| /openbmc/linux/Documentation/driver-api/media/ |
| H A D | tx-rx.rst | 5 Pixel data transmitter and receiver drivers
61 Pixel rate
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