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Searched refs:PWRSEQ0_BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT_MASK (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_5_sh_mask.h44672 #define PWRSEQ0_BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT_MASK … macro
H A Ddcn_3_1_6_sh_mask.h48018 #define PWRSEQ0_BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT_MASK … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_4_2_2_sh_mask.h198 #define PWRSEQ0_BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT_MASK … macro
H A Ddpcs_4_2_3_sh_mask.h215 #define PWRSEQ0_BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT_MASK … macro