Searched refs:PWM_BASE_CLK_MHZ (Results 1 – 1 of 1) sorted by relevance
24 #define PWM_BASE_CLK_MHZ 6 /* 6 MHz */ macro46 clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_USEC); in crc_pwm_calc_clk_div()147 DIV_ROUND_UP(clk_div * NSEC_PER_USEC * 256, PWM_BASE_CLK_MHZ); in crc_pwm_get_state()