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Searched refs:PUP_RL_MODE (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_read_leveling.c106 ddr3_read_pup_reg(PUP_RL_MODE, cs, in ddr3_read_leveling_hw()
120 ddr3_read_pup_reg(PUP_RL_MODE + 0x1, in ddr3_read_leveling_hw()
292 ddr3_write_pup_reg(PUP_RL_MODE, cs, pup_num, phase, in ddr3_read_leveling_sw()
442 ddr3_write_pup_reg(PUP_RL_MODE, cs, PUP_BC, phase, delay); in ddr3_read_leveling_single_cs_rl_mode()
731 reg = ddr3_read_pup_reg(PUP_RL_MODE + 0x1, cs, pup); in ddr3_read_leveling_single_cs_rl_mode()
796 ddr3_write_pup_reg(PUP_RL_MODE, cs, PUP_BC, phase, delay); in ddr3_read_leveling_single_cs_window_mode()
1206 reg = ddr3_read_pup_reg(PUP_RL_MODE + 0x1, cs, pup); in ddr3_read_leveling_single_cs_window_mode()
H A Dddr3_hw_training.c572 if (mode == PUP_RL_MODE) { in ddr3_write_pup_reg()
705 mode_config[RL_MODE_] = PUP_RL_MODE; in ddr3_save_training()
1054 reg = ddr3_read_pup_reg(PUP_RL_MODE, cs, pup); in ddr3_get_min_max_rl_phase()
H A Dddr3_hw_training.h147 #define PUP_RL_MODE 0x2 macro