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Searched refs:PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT (Results 1 – 3 of 3) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_4_sh_mask.h151 #define PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT … macro
H A Dnbio_4_3_0_sh_mask.h34412 #define PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT … macro
H A Dnbio_6_1_sh_mask.h151 #define PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT … macro