1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * From Coreboot file of the same name 4 * 5 * Copyright (C) 2011 The ChromiumOS Authors. 6 */ 7 8 #ifndef _ASM_ARCH_MODEL_206AX_H 9 #define _ASM_ARCH_MODEL_206AX_H 10 11 /* SandyBridge/IvyBridge bus clock is fixed at 100MHz */ 12 #define SANDYBRIDGE_BCLK 100 13 14 #define CPUID_VMX (1 << 5) 15 #define CPUID_SMX (1 << 6) 16 #define MSR_FEATURE_CONFIG 0x13c 17 #define IA32_PLATFORM_DCA_CAP 0x1f8 18 #define IA32_MISC_ENABLE 0x1a0 19 #define MSR_TEMPERATURE_TARGET 0x1a2 20 #define IA32_THERM_INTERRUPT 0x19b 21 #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 22 #define ENERGY_POLICY_PERFORMANCE 0 23 #define ENERGY_POLICY_NORMAL 6 24 #define ENERGY_POLICY_POWERSAVE 15 25 #define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 26 #define MSR_LT_LOCK_MEMORY 0x2e7 27 #define IA32_MC0_STATUS 0x401 28 29 #define MSR_MISC_PWR_MGMT 0x1aa 30 #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) 31 32 #define MSR_PKGC3_IRTL 0x60a 33 #define MSR_PKGC6_IRTL 0x60b 34 #define MSR_PKGC7_IRTL 0x60c 35 #define IRTL_VALID (1 << 15) 36 #define IRTL_1_NS (0 << 10) 37 #define IRTL_32_NS (1 << 10) 38 #define IRTL_1024_NS (2 << 10) 39 #define IRTL_32768_NS (3 << 10) 40 #define IRTL_1048576_NS (4 << 10) 41 #define IRTL_33554432_NS (5 << 10) 42 #define IRTL_RESPONSE_MASK (0x3ff) 43 44 #define MSR_PP0_CURRENT_CONFIG 0x601 45 #define PP0_CURRENT_LIMIT (112 << 3) /* 112 A */ 46 #define MSR_PP1_CURRENT_CONFIG 0x602 47 #define PP1_CURRENT_LIMIT_SNB (35 << 3) /* 35 A */ 48 #define PP1_CURRENT_LIMIT_IVB (50 << 3) /* 50 A */ 49 #define MSR_PKG_POWER_SKU 0x614 50 51 #define IVB_CONFIG_TDP_MIN_CPUID 0x306a2 52 #define MSR_CONFIG_TDP_LEVEL1 0x649 53 #define MSR_CONFIG_TDP_LEVEL2 0x64a 54 #define MSR_CONFIG_TDP_CONTROL 0x64b 55 56 /* P-state configuration */ 57 #define PSS_MAX_ENTRIES 8 58 #define PSS_RATIO_STEP 2 59 #define PSS_LATENCY_TRANSITION 10 60 #define PSS_LATENCY_BUSMASTER 10 61 62 /* Configure power limits for turbo mode */ 63 void set_power_limits(u8 power_limit_1_time); 64 int cpu_config_tdp_levels(void); 65 66 #endif 67