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Searched refs:PRV_U (Results 1 – 10 of 10) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dop_helper.c289 mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U); in helper_sret()
349 riscv_has_ext(env, RVU) ? PRV_U : PRV_M); in helper_mret()
377 bool prv_u = env->priv == PRV_U; in helper_wfi()
395 if (env->virt_enabled && (env->priv == PRV_S || env->priv == PRV_U) && in helper_wrs_nto()
408 (env->priv == PRV_U || in helper_tlb_flush()
412 (env->priv == PRV_U || get_field(env->hstatus, HSTATUS_VTVM))) { in helper_tlb_flush()
458 } else if (env->priv == PRV_U && !get_field(env->hstatus, HSTATUS_HU)) { in check_access_hlsv()
H A Dpmu.c116 (env->priv == PRV_U && virt_on && in riscv_pmu_incr_ctr_rv32()
120 (env->priv == PRV_U && !virt_on && in riscv_pmu_incr_ctr_rv32()
157 (env->priv == PRV_U && virt_on && in riscv_pmu_incr_ctr_rv64()
161 (env->priv == PRV_U && !virt_on && in riscv_pmu_incr_ctr_rv64()
H A Dcpu_helper.c76 case PRV_U: in cpu_get_fcfien()
103 case PRV_U: in cpu_get_bcfien()
249 case PRV_U: in riscv_cpu_update_mask()
1181 if (mode != PRV_U) { in get_physical_address()
1911 } else if (env->priv == PRV_U) { in riscv_cpu_do_interrupt()
H A Dcsr.c63 if (env->priv == PRV_U && !(env->sstateen[index] & bit)) { in smstateen_acc_ok()
68 if (env->priv == PRV_U && riscv_has_ext(env, RVS)) { in smstateen_acc_ok()
148 (env->priv == PRV_U && !get_field(env->scounteren, ctr_mask))) { in ctr()
153 if (riscv_has_ext(env, RVS) && env->priv == PRV_U && in ctr()
638 } else if (env->priv == PRV_U && (env->mseccfg & MSECCFG_USEED)) { in seed()
1091 curr_val += counter_arr[PRV_U]; in riscv_pmu_ctr_get_fixed_counters_val()
1099 curr_val += counter_arr_virt[PRV_U]; in riscv_pmu_ctr_get_fixed_counters_val()
1588 case PRV_U: in legalize_mpp()
4386 case PRV_U: in check_pm_current_disabled()
4555 if ((cpu_address_mode(env) == PRV_U) && (env->mmte & U_PM_ENABLE)) { in write_upmmask()
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H A Dcpu_bits.h621 #define PRV_U 0 macro
H A Dcpu.h680 case PRV_U: in cpu_get_xl()
H A Dcpu.c1010 env->priv = PRV_U; in riscv_cpu_reset_hold()
/openbmc/u-boot/arch/riscv/include/asm/
H A Dencoding.h64 #define PRV_U 0 macro
/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_privileged.c.inc55 if (semihosting_enabled(ctx->priv == PRV_U) &&
H A Dtrans_xthead.c.inc272 if (ctx->priv == PRV_U) { \