1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
3 */
4
5 #include <linux/iopoll.h>
6
7 #include "dpu_hw_mdss.h"
8 #include "dpu_hwio.h"
9 #include "dpu_hw_catalog.h"
10 #include "dpu_hw_pingpong.h"
11 #include "dpu_kms.h"
12 #include "dpu_trace.h"
13
14 #define PP_TEAR_CHECK_EN 0x000
15 #define PP_SYNC_CONFIG_VSYNC 0x004
16 #define PP_SYNC_CONFIG_HEIGHT 0x008
17 #define PP_SYNC_WRCOUNT 0x00C
18 #define PP_VSYNC_INIT_VAL 0x010
19 #define PP_INT_COUNT_VAL 0x014
20 #define PP_SYNC_THRESH 0x018
21 #define PP_START_POS 0x01C
22 #define PP_RD_PTR_IRQ 0x020
23 #define PP_WR_PTR_IRQ 0x024
24 #define PP_OUT_LINE_COUNT 0x028
25 #define PP_LINE_COUNT 0x02C
26 #define PP_AUTOREFRESH_CONFIG 0x030
27
28 #define PP_FBC_MODE 0x034
29 #define PP_FBC_BUDGET_CTL 0x038
30 #define PP_FBC_LOSSY_MODE 0x03C
31 #define PP_DSC_MODE 0x0a0
32 #define PP_DCE_DATA_IN_SWAP 0x0ac
33 #define PP_DCE_DATA_OUT_SWAP 0x0c8
34
35 #define PP_DITHER_EN 0x000
36 #define PP_DITHER_BITDEPTH 0x004
37 #define PP_DITHER_MATRIX 0x008
38
39 #define DITHER_DEPTH_MAP_INDEX 9
40
41 static u32 dither_depth_map[DITHER_DEPTH_MAP_INDEX] = {
42 0, 0, 0, 0, 0, 0, 0, 1, 2
43 };
44
dpu_hw_pp_setup_dither(struct dpu_hw_pingpong * pp,struct dpu_hw_dither_cfg * cfg)45 static void dpu_hw_pp_setup_dither(struct dpu_hw_pingpong *pp,
46 struct dpu_hw_dither_cfg *cfg)
47 {
48 struct dpu_hw_blk_reg_map *c;
49 u32 i, base, data = 0;
50
51 c = &pp->hw;
52 base = pp->caps->sblk->dither.base;
53 if (!cfg) {
54 DPU_REG_WRITE(c, base + PP_DITHER_EN, 0);
55 return;
56 }
57
58 data = dither_depth_map[cfg->c0_bitdepth] & REG_MASK(2);
59 data |= (dither_depth_map[cfg->c1_bitdepth] & REG_MASK(2)) << 2;
60 data |= (dither_depth_map[cfg->c2_bitdepth] & REG_MASK(2)) << 4;
61 data |= (dither_depth_map[cfg->c3_bitdepth] & REG_MASK(2)) << 6;
62 data |= (cfg->temporal_en) ? (1 << 8) : 0;
63
64 DPU_REG_WRITE(c, base + PP_DITHER_BITDEPTH, data);
65
66 for (i = 0; i < DITHER_MATRIX_SZ - 3; i += 4) {
67 data = (cfg->matrix[i] & REG_MASK(4)) |
68 ((cfg->matrix[i + 1] & REG_MASK(4)) << 4) |
69 ((cfg->matrix[i + 2] & REG_MASK(4)) << 8) |
70 ((cfg->matrix[i + 3] & REG_MASK(4)) << 12);
71 DPU_REG_WRITE(c, base + PP_DITHER_MATRIX + i, data);
72 }
73 DPU_REG_WRITE(c, base + PP_DITHER_EN, 1);
74 }
75
dpu_hw_pp_enable_te(struct dpu_hw_pingpong * pp,struct dpu_hw_tear_check * te)76 static int dpu_hw_pp_enable_te(struct dpu_hw_pingpong *pp,
77 struct dpu_hw_tear_check *te)
78 {
79 struct dpu_hw_blk_reg_map *c;
80 int cfg;
81
82 if (!pp || !te)
83 return -EINVAL;
84 c = &pp->hw;
85
86 cfg = BIT(19); /*VSYNC_COUNTER_EN */
87 if (te->hw_vsync_mode)
88 cfg |= BIT(20);
89
90 cfg |= te->vsync_count;
91
92 DPU_REG_WRITE(c, PP_SYNC_CONFIG_VSYNC, cfg);
93 DPU_REG_WRITE(c, PP_SYNC_CONFIG_HEIGHT, te->sync_cfg_height);
94 DPU_REG_WRITE(c, PP_VSYNC_INIT_VAL, te->vsync_init_val);
95 DPU_REG_WRITE(c, PP_RD_PTR_IRQ, te->rd_ptr_irq);
96 DPU_REG_WRITE(c, PP_START_POS, te->start_pos);
97 DPU_REG_WRITE(c, PP_SYNC_THRESH,
98 ((te->sync_threshold_continue << 16) |
99 te->sync_threshold_start));
100 DPU_REG_WRITE(c, PP_SYNC_WRCOUNT,
101 (te->start_pos + te->sync_threshold_start + 1));
102
103 DPU_REG_WRITE(c, PP_TEAR_CHECK_EN, 1);
104
105 return 0;
106 }
107
dpu_hw_pp_setup_autorefresh_config(struct dpu_hw_pingpong * pp,u32 frame_count,bool enable)108 static void dpu_hw_pp_setup_autorefresh_config(struct dpu_hw_pingpong *pp,
109 u32 frame_count, bool enable)
110 {
111 DPU_REG_WRITE(&pp->hw, PP_AUTOREFRESH_CONFIG,
112 enable ? (BIT(31) | frame_count) : 0);
113 }
114
115 /*
116 * dpu_hw_pp_get_autorefresh_config - Get autorefresh config from HW
117 * @pp: DPU pingpong structure
118 * @frame_count: Used to return the current frame count from hw
119 *
120 * Returns: True if autorefresh enabled, false if disabled.
121 */
dpu_hw_pp_get_autorefresh_config(struct dpu_hw_pingpong * pp,u32 * frame_count)122 static bool dpu_hw_pp_get_autorefresh_config(struct dpu_hw_pingpong *pp,
123 u32 *frame_count)
124 {
125 u32 val = DPU_REG_READ(&pp->hw, PP_AUTOREFRESH_CONFIG);
126 if (frame_count != NULL)
127 *frame_count = val & 0xffff;
128 return !!((val & BIT(31)) >> 31);
129 }
130
dpu_hw_pp_disable_te(struct dpu_hw_pingpong * pp)131 static int dpu_hw_pp_disable_te(struct dpu_hw_pingpong *pp)
132 {
133 struct dpu_hw_blk_reg_map *c;
134
135 if (!pp)
136 return -EINVAL;
137 c = &pp->hw;
138
139 DPU_REG_WRITE(c, PP_TEAR_CHECK_EN, 0);
140 return 0;
141 }
142
dpu_hw_pp_connect_external_te(struct dpu_hw_pingpong * pp,bool enable_external_te)143 static int dpu_hw_pp_connect_external_te(struct dpu_hw_pingpong *pp,
144 bool enable_external_te)
145 {
146 struct dpu_hw_blk_reg_map *c = &pp->hw;
147 u32 cfg;
148 int orig;
149
150 if (!pp)
151 return -EINVAL;
152
153 c = &pp->hw;
154 cfg = DPU_REG_READ(c, PP_SYNC_CONFIG_VSYNC);
155 orig = (bool)(cfg & BIT(20));
156 if (enable_external_te)
157 cfg |= BIT(20);
158 else
159 cfg &= ~BIT(20);
160 DPU_REG_WRITE(c, PP_SYNC_CONFIG_VSYNC, cfg);
161 trace_dpu_pp_connect_ext_te(pp->idx - PINGPONG_0, cfg);
162
163 return orig;
164 }
165
dpu_hw_pp_get_vsync_info(struct dpu_hw_pingpong * pp,struct dpu_hw_pp_vsync_info * info)166 static int dpu_hw_pp_get_vsync_info(struct dpu_hw_pingpong *pp,
167 struct dpu_hw_pp_vsync_info *info)
168 {
169 struct dpu_hw_blk_reg_map *c;
170 u32 val;
171
172 if (!pp || !info)
173 return -EINVAL;
174 c = &pp->hw;
175
176 val = DPU_REG_READ(c, PP_VSYNC_INIT_VAL);
177 info->rd_ptr_init_val = val & 0xffff;
178
179 val = DPU_REG_READ(c, PP_INT_COUNT_VAL);
180 info->rd_ptr_frame_count = (val & 0xffff0000) >> 16;
181 info->rd_ptr_line_count = val & 0xffff;
182
183 val = DPU_REG_READ(c, PP_LINE_COUNT);
184 info->wr_ptr_line_count = val & 0xffff;
185
186 return 0;
187 }
188
dpu_hw_pp_get_line_count(struct dpu_hw_pingpong * pp)189 static u32 dpu_hw_pp_get_line_count(struct dpu_hw_pingpong *pp)
190 {
191 struct dpu_hw_blk_reg_map *c = &pp->hw;
192 u32 height, init;
193 u32 line = 0xFFFF;
194
195 if (!pp)
196 return 0;
197 c = &pp->hw;
198
199 init = DPU_REG_READ(c, PP_VSYNC_INIT_VAL) & 0xFFFF;
200 height = DPU_REG_READ(c, PP_SYNC_CONFIG_HEIGHT) & 0xFFFF;
201
202 if (height < init)
203 return line;
204
205 line = DPU_REG_READ(c, PP_INT_COUNT_VAL) & 0xFFFF;
206
207 if (line < init)
208 line += (0xFFFF - init);
209 else
210 line -= init;
211
212 return line;
213 }
214
dpu_hw_pp_disable_autorefresh(struct dpu_hw_pingpong * pp,uint32_t encoder_id,u16 vdisplay)215 static void dpu_hw_pp_disable_autorefresh(struct dpu_hw_pingpong *pp,
216 uint32_t encoder_id, u16 vdisplay)
217 {
218 struct dpu_hw_pp_vsync_info info;
219 int trial = 0;
220
221 /* If autorefresh is already disabled, we have nothing to do */
222 if (!dpu_hw_pp_get_autorefresh_config(pp, NULL))
223 return;
224
225 /*
226 * If autorefresh is enabled, disable it and make sure it is safe to
227 * proceed with current frame commit/push. Sequence followed is,
228 * 1. Disable TE
229 * 2. Disable autorefresh config
230 * 4. Poll for frame transfer ongoing to be false
231 * 5. Enable TE back
232 */
233
234 dpu_hw_pp_connect_external_te(pp, false);
235 dpu_hw_pp_setup_autorefresh_config(pp, 0, false);
236
237 do {
238 udelay(DPU_ENC_MAX_POLL_TIMEOUT_US);
239 if ((trial * DPU_ENC_MAX_POLL_TIMEOUT_US)
240 > (KICKOFF_TIMEOUT_MS * USEC_PER_MSEC)) {
241 DPU_ERROR("enc%d pp%d disable autorefresh failed\n",
242 encoder_id, pp->idx - PINGPONG_0);
243 break;
244 }
245
246 trial++;
247
248 dpu_hw_pp_get_vsync_info(pp, &info);
249 } while (info.wr_ptr_line_count > 0 &&
250 info.wr_ptr_line_count < vdisplay);
251
252 dpu_hw_pp_connect_external_te(pp, true);
253
254 DPU_DEBUG("enc%d pp%d disabled autorefresh\n",
255 encoder_id, pp->idx - PINGPONG_0);
256 }
257
dpu_hw_pp_dsc_enable(struct dpu_hw_pingpong * pp)258 static int dpu_hw_pp_dsc_enable(struct dpu_hw_pingpong *pp)
259 {
260 struct dpu_hw_blk_reg_map *c = &pp->hw;
261
262 DPU_REG_WRITE(c, PP_DSC_MODE, 1);
263 return 0;
264 }
265
dpu_hw_pp_dsc_disable(struct dpu_hw_pingpong * pp)266 static void dpu_hw_pp_dsc_disable(struct dpu_hw_pingpong *pp)
267 {
268 struct dpu_hw_blk_reg_map *c = &pp->hw;
269
270 DPU_REG_WRITE(c, PP_DSC_MODE, 0);
271 }
272
dpu_hw_pp_setup_dsc(struct dpu_hw_pingpong * pp)273 static int dpu_hw_pp_setup_dsc(struct dpu_hw_pingpong *pp)
274 {
275 struct dpu_hw_blk_reg_map *pp_c = &pp->hw;
276 int data;
277
278 data = DPU_REG_READ(pp_c, PP_DCE_DATA_OUT_SWAP);
279 data |= BIT(18); /* endian flip */
280 DPU_REG_WRITE(pp_c, PP_DCE_DATA_OUT_SWAP, data);
281 return 0;
282 }
283
_setup_pingpong_ops(struct dpu_hw_pingpong * c,unsigned long features)284 static void _setup_pingpong_ops(struct dpu_hw_pingpong *c,
285 unsigned long features)
286 {
287 if (test_bit(DPU_PINGPONG_TE, &features)) {
288 c->ops.enable_tearcheck = dpu_hw_pp_enable_te;
289 c->ops.disable_tearcheck = dpu_hw_pp_disable_te;
290 c->ops.connect_external_te = dpu_hw_pp_connect_external_te;
291 c->ops.get_line_count = dpu_hw_pp_get_line_count;
292 c->ops.disable_autorefresh = dpu_hw_pp_disable_autorefresh;
293 }
294
295 if (test_bit(DPU_PINGPONG_DSC, &features)) {
296 c->ops.setup_dsc = dpu_hw_pp_setup_dsc;
297 c->ops.enable_dsc = dpu_hw_pp_dsc_enable;
298 c->ops.disable_dsc = dpu_hw_pp_dsc_disable;
299 }
300
301 if (test_bit(DPU_PINGPONG_DITHER, &features))
302 c->ops.setup_dither = dpu_hw_pp_setup_dither;
303 };
304
dpu_hw_pingpong_init(const struct dpu_pingpong_cfg * cfg,void __iomem * addr)305 struct dpu_hw_pingpong *dpu_hw_pingpong_init(const struct dpu_pingpong_cfg *cfg,
306 void __iomem *addr)
307 {
308 struct dpu_hw_pingpong *c;
309
310 c = kzalloc(sizeof(*c), GFP_KERNEL);
311 if (!c)
312 return ERR_PTR(-ENOMEM);
313
314 c->hw.blk_addr = addr + cfg->base;
315 c->hw.log_mask = DPU_DBG_MASK_PINGPONG;
316
317 c->idx = cfg->id;
318 c->caps = cfg;
319 _setup_pingpong_ops(c, c->caps->features);
320
321 return c;
322 }
323
dpu_hw_pingpong_destroy(struct dpu_hw_pingpong * pp)324 void dpu_hw_pingpong_destroy(struct dpu_hw_pingpong *pp)
325 {
326 kfree(pp);
327 }
328