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Searched refs:PPC_BIT32 (Results 1 – 10 of 10) sorted by relevance

/openbmc/qemu/include/hw/ppc/
H A Dxive2_regs.h22 #define TM2_QW0W2_VU PPC_BIT32(0)
24 #define TM2_QW1W2_VO PPC_BIT32(0)
25 #define TM2_QW1W2_HO PPC_BIT32(1)
27 #define TM2_QW2W2_VP PPC_BIT32(0)
28 #define TM2_QW2W2_HP PPC_BIT32(1)
30 #define TM2_QW3W2_VT PPC_BIT32(0)
31 #define TM2_QW3W2_HT PPC_BIT32(1)
32 #define TM2_QW3W2_LP PPC_BIT32(6)
33 #define TM2_QW3W2_LE PPC_BIT32(7)
76 #define END2_W1_ESn_P PPC_BIT32(0)
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H A Dxive_regs.h91 #define TM_QW0W2_VU PPC_BIT32(0)
93 #define TM_QW1W2_VO PPC_BIT32(0)
95 #define TM_QW2W2_VP PPC_BIT32(0)
97 #define TM_QW3W2_VT PPC_BIT32(0)
98 #define TM_QW3W2_LP PPC_BIT32(6)
99 #define TM_QW3W2_LE PPC_BIT32(7)
100 #define TM_QW3W2_T PPC_BIT32(31)
217 #define END_W1_ESn_P PPC_BIT32(0)
218 #define END_W1_ESn_Q PPC_BIT32(1)
220 #define END_W1_ESe_P PPC_BIT32(2)
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/openbmc/linux/arch/powerpc/include/asm/
H A Dxive-regs.h80 #define TM_QW0W2_VU PPC_BIT32(0)
82 #define TM_QW1W2_VO PPC_BIT32(0)
83 #define TM_QW1W2_HO PPC_BIT32(1) /* P10 XIVE2 */
85 #define TM_QW2W2_VP PPC_BIT32(0)
86 #define TM_QW2W2_HP PPC_BIT32(1) /* P10 XIVE2 */
88 #define TM_QW3W2_VT PPC_BIT32(0)
89 #define TM_QW3W2_HT PPC_BIT32(1) /* P10 XIVE2 */
90 #define TM_QW3W2_LP PPC_BIT32(6)
91 #define TM_QW3W2_LE PPC_BIT32(7)
92 #define TM_QW3W2_T PPC_BIT32(31)
H A Dplpks.h18 #define PLPKS_OSSECBOOTAUDIT PPC_BIT32(1) // OS secure boot must be audit/enforce
19 #define PLPKS_OSSECBOOTENFORCE PPC_BIT32(2) // OS secure boot must be enforce
20 #define PLPKS_PWSET PPC_BIT32(3) // No access without password set
21 #define PLPKS_WORLDREADABLE PPC_BIT32(4) // Readable without authentication
22 #define PLPKS_IMMUTABLE PPC_BIT32(5) // Once written, object cannot be removed
23 #define PLPKS_TRANSIENT PPC_BIT32(6) // Object does not persist through reboot
24 #define PLPKS_SIGNEDUPDATE PPC_BIT32(7) // Object can only be modified by signed updates
25 #define PLPKS_HVPROVISIONED PPC_BIT32(28) // Hypervisor has provisioned this object
H A Dbitops.h55 #define PPC_BIT32(bit) (1UL << PPC_BITLSHIFT32(bit)) macro
56 #define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be))|PPC_BIT32(bs))
/openbmc/skeleton/op-hostctl/
H A Dcontrol_host_obj.c20 #define PPC_BIT32(bit) (0x80000000UL >> (bit)) macro
37 #define SBE_WARMSTART PPC_BIT32(0)
38 #define SBE_HW_TRIGGER PPC_BIT32(2)
39 #define SBE_UPDATE_1ST_NIBBLE PPC_BIT32(3)
40 #define SBE_IMAGE_SELECT PPC_BIT32(8)
41 #define SBE_UPDATE_3RD_NIBBLE PPC_BIT32(11)
/openbmc/qemu/tests/qtest/
H A Dpnv-host-i2c-test.c16 #define PPC_BIT32(bit) (0x80000000 >> (bit)) macro
19 #define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be)) | \
20 PPC_BIT32(bs))
/openbmc/qemu/target/ppc/
H A Dcpu.h44 #define PPC_BIT32(bit) (0x80000000 >> (bit)) macro
47 #define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be)) | \
48 PPC_BIT32(bs))
/openbmc/qemu/hw/ppc/
H A Dpnv_core.c636 if (offset & PPC_BIT32(16 + i)) { in pnv_qme_power10_xscom_write()
/openbmc/qemu/target/ppc/translate/
H A Dvsx-impl.c.inc1456 if (ctx->opcode & PPC_BIT32(25)) { \