| /openbmc/openpower-occ-control/ |
| H A D | occ_status.hpp | 16 #ifdef POWER10
89 #ifdef POWER10 in Status()
103 #ifdef POWER10 in Status()
114 #ifdef POWER10 in Status()
130 #ifdef POWER10 in Status()
200 #ifdef POWER10
296 #ifdef POWER10
315 #ifdef POWER10
345 #ifdef POWER10
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| H A D | occ_device.hpp | 50 #ifdef POWER10 in Device()
85 #ifdef POWER10 in Device()
108 #ifdef POWER10 in addErrorWatch()
123 #ifdef POWER10 in addErrorWatch()
165 #ifdef POWER10 in removeErrorWatch()
225 #ifdef POWER10
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| H A D | occ_manager.hpp | 14 #ifdef POWER10
47 #ifndef POWER10
96 #ifdef POWER10 in Manager()
222 #ifdef POWER10
341 #ifdef POWER10
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| H A D | occ_manager.cpp | 83 #ifndef POWER10 in findAndCreateObjects()
190 #ifdef POWER10
368 #ifdef POWER10 in createObjects()
395 #ifdef POWER10 in createObjects()
403 #ifdef POWER10 in createObjects()
468 #ifdef POWER10 in statusCallBack()
478 #ifdef POWER10 in statusCallBack()
556 #ifdef POWER10 in statusCallBack()
576 #ifdef POWER10 in statusCallBack()
605 #ifdef POWER10 in initStatusObjects()
[all …]
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| H A D | app.cpp | 7 #ifdef POWER10
42 #ifdef POWER10 in main()
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| H A D | occ_pass_through.hpp | 44 #ifdef POWER10
75 #ifdef POWER10
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| H A D | occ_pass_through.cpp | 26 #ifdef POWER10 in PassThrough()
32 #ifdef POWER10 in PassThrough()
135 #ifdef POWER10 in setMode()
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| H A D | occ_status.cpp | 73 #ifdef POWER10 in occActive()
150 #ifdef POWER10 in deviceError()
240 #ifdef POWER10
462 #ifdef POWER10 in occReadStateNow()
521 #ifdef POWER10 in occReadStateNow()
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| H A D | powermode.hpp | 5 #ifdef POWER10
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| H A D | meson.build | 54 conf_data.set('POWER10', get_option('power10-support').allowed())
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| /openbmc/openbmc/poky/meta/recipes-devtools/binutils/binutils/ |
| H A D | 0007-fix-the-incorrect-assembling-for-ppc-wait-mnemonic.patch | 22 {"waitrsv", XWCPL(31,30,1,0),0xffffffff, POWER10, EXT, {0}},
23 {"pause_short", XWCPL(31,30,2,0),0xffffffff, POWER10, EXT, {0}},
24 -{"wait", X(31,30), XWCPL_MASK, POWER10, 0, {WC, PL}},
25 -{"wait", X(31,30), XWC_MASK, POWER9, POWER10, {WC}},
34 +{"wait", X(31,62), XWC_MASK, E500MC|PPCA2|POWER9|POWER10, 0, {WC}},
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| /openbmc/openpower-occ-control/test/ |
| H A D | error_files_tests.cpp | 29 #ifdef POWER10 in ErrorFiles()
83 #ifdef POWER10
98 #ifdef POWER10 in TEST_F()
109 #ifndef POWER10
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| H A D | utest.cpp | 20 #ifdef POWER10 in VerifyOccInput()
38 #ifdef POWER10
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| /openbmc/linux/tools/testing/selftests/powerpc/pmu/sampling_tests/ |
| H A D | misc.h | 11 #define POWER10 0x80 macro
168 if (pvr == POWER10) in get_mmcr2_l2l3()
175 if (pvr != POWER10) in get_mmcr3_src()
182 if (pvr == POWER10) in get_mmcra_thd_cmp()
194 if (pvr == POWER10) in get_mmcra_bhrb_disable()
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| H A D | misc.c | 62 case POWER10: in init_ev_encodes()
132 if ((pvr != POWER10) && (pvr != POWER9)) in platform_check_for_tests()
501 base_pvr = POWER10; in auxv_generic_compat_pmu()
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| H A D | bhrb_filter_map_test.c | 86 if (PVR_VER(mfspr(SPRN_PVR)) == POWER10) { in bhrb_filter_map_test()
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| /openbmc/qemu/tests/tcg/ppc64/ |
| H A D | Makefile.target | 43 run-byte_reverse: QEMU_OPTS+=-cpu POWER10
49 run-sha512-vector: QEMU_OPTS+=-cpu POWER10
52 run-vector: QEMU_OPTS += -cpu POWER10
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| /openbmc/linux/tools/testing/selftests/powerpc/pmu/event_code_tests/ |
| H A D | reserved_bits_mmcra_sample_elig_mode_test.c | 62 if (PVR_VER(mfspr(SPRN_PVR)) == POWER10) { in reserved_bits_mmcra_sample_elig_mode()
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| H A D | event_alternatives_tests_p10.c | 39 SKIP_IF(PVR_VER(mfspr(SPRN_PVR)) != POWER10); in event_alternatives_tests_p10()
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| H A D | generic_events_valid_test.c | 34 if (PVR_VER(mfspr(SPRN_PVR)) == POWER10) { in generic_events_valid_test()
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| /openbmc/linux/Documentation/devicetree/bindings/fsi/ |
| H A D | ibm,p9-occ.txt | 1 Device-tree bindings for FSI-attached POWER9/POWER10 On-Chip Controller (OCC)
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| /openbmc/linux/arch/powerpc/platforms/book3s/ |
| H A D | Kconfig | 13 and POWER10 PowerVM platforms.
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| /openbmc/linux/Documentation/powerpc/ |
| H A D | cpu_families.rst | 115 | POWER10 |
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| /openbmc/linux/arch/powerpc/platforms/ |
| H A D | Kconfig.cputype | 181 bool "POWER10"
439 MMU. From POWER10 radix is also supported by PowerVM.
473 POWER10 and later CPUs support prefixed instructions, 8 byte
491 POWER10 and later CPUs support pc relative addressing. Recent
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| /openbmc/qemu/target/ppc/translate/ |
| H A D | misc-impl.c.inc | 60 /* lwsync, or plwsync on POWER10 and later */
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