Searched refs:PORT_PLL_P1_MASK (Results 1 – 3 of 3) sorted by relevance
1946 PORT_PLL_P1_MASK | PORT_PLL_P2_MASK, pll->state.hw_state.ebb0); in bxt_ddi_pll_enable()2062 hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK; in bxt_ddi_pll_get_hw_state()2247 clock.p1 = REG_FIELD_GET(PORT_PLL_P1_MASK, pll_state->ebb0); in bxt_ddi_pll_get_freq()
596 #define PORT_PLL_P1_MASK REG_GENMASK(15, 13) macro597 #define PORT_PLL_P1(p1) REG_FIELD_PREP(PORT_PLL_P1_MASK, (p1))
578 clock.p1 = REG_FIELD_GET(PORT_PLL_P1_MASK, in bxt_vgpu_get_dp_bitrate()