xref: /openbmc/linux/drivers/pinctrl/renesas/sh_pfc.h (revision b88e733a)
1 /* SPDX-License-Identifier: GPL-2.0
2  *
3  * SuperH Pin Function Controller Support
4  *
5  * Copyright (c) 2008 Magnus Damm
6  */
7 
8 #ifndef __SH_PFC_H
9 #define __SH_PFC_H
10 
11 #include <linux/bug.h>
12 #include <linux/pinctrl/pinconf-generic.h>
13 #include <linux/spinlock.h>
14 #include <linux/stringify.h>
15 
16 enum {
17 	PINMUX_TYPE_NONE,
18 	PINMUX_TYPE_FUNCTION,
19 	PINMUX_TYPE_GPIO,
20 	PINMUX_TYPE_OUTPUT,
21 	PINMUX_TYPE_INPUT,
22 };
23 
24 #define SH_PFC_PIN_NONE			U16_MAX
25 
26 #define SH_PFC_PIN_CFG_INPUT		(1 << 0)
27 #define SH_PFC_PIN_CFG_OUTPUT		(1 << 1)
28 #define SH_PFC_PIN_CFG_PULL_UP		(1 << 2)
29 #define SH_PFC_PIN_CFG_PULL_DOWN	(1 << 3)
30 #define SH_PFC_PIN_CFG_PULL_UP_DOWN	(SH_PFC_PIN_CFG_PULL_UP | \
31 					 SH_PFC_PIN_CFG_PULL_DOWN)
32 
33 #define SH_PFC_PIN_CFG_IO_VOLTAGE_MASK	GENMASK(5, 4)
34 #define SH_PFC_PIN_CFG_IO_VOLTAGE_18_25	(1 << 4)
35 #define SH_PFC_PIN_CFG_IO_VOLTAGE_18_33	(2 << 4)
36 #define SH_PFC_PIN_CFG_IO_VOLTAGE_25_33	(3 << 4)
37 
38 #define SH_PFC_PIN_CFG_DRIVE_STRENGTH	(1 << 6)
39 
40 #define SH_PFC_PIN_CFG_NO_GPIO		(1 << 31)
41 
42 struct sh_pfc_pin {
43 	const char *name;
44 	unsigned int configs;
45 	u16 pin;
46 	u16 enum_id;
47 };
48 
49 #define SH_PFC_PIN_GROUP_ALIAS(alias, _name) {				\
50 	.name = #alias,							\
51 	.pins = _name##_pins,						\
52 	.mux = _name##_mux,						\
53 	.nr_pins = ARRAY_SIZE(_name##_pins) +				\
54 	BUILD_BUG_ON_ZERO(sizeof(_name##_pins) != sizeof(_name##_mux)),	\
55 }
56 #define SH_PFC_PIN_GROUP(name)	SH_PFC_PIN_GROUP_ALIAS(name, name)
57 
58 /*
59  * Define a pin group referring to a subset of an array of pins.
60  */
61 #define SH_PFC_PIN_GROUP_SUBSET(_name, data, first, n) {		\
62 	.name = #_name,							\
63 	.pins = data##_pins + first,					\
64 	.mux = data##_mux + first,					\
65 	.nr_pins = n +							\
66 	BUILD_BUG_ON_ZERO(first + n > ARRAY_SIZE(data##_pins)) +	\
67 	BUILD_BUG_ON_ZERO(first + n > ARRAY_SIZE(data##_mux)),		\
68 }
69 
70 /*
71  * Define a pin group for the data pins of a resizable bus.
72  * An optional 'suffix' argument is accepted, to be used when the same group
73  * can appear on a different set of pins.
74  */
75 #define BUS_DATA_PIN_GROUP(base, n, ...)				\
76 	SH_PFC_PIN_GROUP_SUBSET(base##n##__VA_ARGS__, base##__VA_ARGS__, 0, n)
77 
78 struct sh_pfc_pin_group {
79 	const char *name;
80 	const unsigned int *pins;
81 	const unsigned int *mux;
82 	unsigned int nr_pins;
83 };
84 
85 #define SH_PFC_FUNCTION(n) {						\
86 	.name = #n,							\
87 	.groups = n##_groups,						\
88 	.nr_groups = ARRAY_SIZE(n##_groups),				\
89 }
90 
91 struct sh_pfc_function {
92 	const char *name;
93 	const char * const *groups;
94 	unsigned int nr_groups;
95 };
96 
97 struct pinmux_func {
98 	u16 enum_id;
99 	const char *name;
100 };
101 
102 struct pinmux_cfg_reg {
103 	u32 reg;
104 	u8 reg_width, field_width;
105 #ifdef DEBUG
106 	u16 nr_enum_ids;	/* for variable width regs only */
107 #define SET_NR_ENUM_IDS(n)	.nr_enum_ids = n,
108 #else
109 #define SET_NR_ENUM_IDS(n)
110 #endif
111 	const u16 *enum_ids;
112 	const s8 *var_field_width;
113 };
114 
115 #define GROUP(...)	__VA_ARGS__
116 
117 /*
118  * Describe a config register consisting of several fields of the same width
119  *   - name: Register name (unused, for documentation purposes only)
120  *   - r: Physical register address
121  *   - r_width: Width of the register (in bits)
122  *   - f_width: Width of the fixed-width register fields (in bits)
123  *   - ids: For each register field (from left to right, i.e. MSB to LSB),
124  *          2^f_width enum IDs must be specified, one for each possible
125  *          combination of the register field bit values, all wrapped using
126  *          the GROUP() macro.
127  */
128 #define PINMUX_CFG_REG(name, r, r_width, f_width, ids)			\
129 	.reg = r, .reg_width = r_width,					\
130 	.field_width = f_width + BUILD_BUG_ON_ZERO(r_width % f_width) +	\
131 	BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \
132 			  (r_width / f_width) << f_width),		\
133 	.enum_ids = (const u16 [(r_width / f_width) << f_width]) { ids }
134 
135 /*
136  * Describe a config register consisting of several fields of different widths
137  *   - name: Register name (unused, for documentation purposes only)
138  *   - r: Physical register address
139  *   - r_width: Width of the register (in bits)
140  *   - f_widths: List of widths of the register fields (in bits), from left
141  *               to right (i.e. MSB to LSB), wrapped using the GROUP() macro.
142  *               Reserved fields are indicated by negating the field width.
143  *   - ids: For each non-reserved register field (from left to right, i.e. MSB
144  *          to LSB), 2^f_widths[i] enum IDs must be specified, one for each
145  *          possible combination of the register field bit values, all wrapped
146  *          using the GROUP() macro.
147  */
148 #define PINMUX_CFG_REG_VAR(name, r, r_width, f_widths, ids)		\
149 	.reg = r, .reg_width = r_width,					\
150 	.var_field_width = (const s8 []) { f_widths, 0 },		\
151 	SET_NR_ENUM_IDS(sizeof((const u16 []) { ids }) / sizeof(u16))	\
152 	.enum_ids = (const u16 []) { ids }
153 
154 struct pinmux_drive_reg_field {
155 	u16 pin;
156 	u8 offset;
157 	u8 size;
158 };
159 
160 struct pinmux_drive_reg {
161 	u32 reg;
162 	const struct pinmux_drive_reg_field fields[10];
163 };
164 
165 #define PINMUX_DRIVE_REG(name, r) \
166 	.reg = r, \
167 	.fields =
168 
169 struct pinmux_bias_reg {	/* At least one of puen/pud must exist */
170 	u32 puen;		/* Pull-enable or pull-up control register */
171 	u32 pud;		/* Pull-up/down or pull-down control register */
172 	const u16 pins[32];
173 };
174 
175 #define PINMUX_BIAS_REG(name1, r1, name2, r2) \
176 	.puen = r1,	\
177 	.pud = r2,	\
178 	.pins =
179 
180 struct pinmux_ioctrl_reg {
181 	u32 reg;
182 };
183 
184 struct pinmux_data_reg {
185 	u32 reg;
186 	u8 reg_width;
187 	const u16 *enum_ids;
188 };
189 
190 /*
191  * Describe a data register
192  *   - name: Register name (unused, for documentation purposes only)
193  *   - r: Physical register address
194  *   - r_width: Width of the register (in bits)
195  *   - ids: For each register bit (from left to right, i.e. MSB to LSB), one
196  *          enum ID must be specified, all wrapped using the GROUP() macro.
197  */
198 #define PINMUX_DATA_REG(name, r, r_width, ids)				\
199 	.reg = r, .reg_width = r_width +				\
200 	BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \
201 			  r_width),					\
202 	.enum_ids = (const u16 [r_width]) { ids }
203 
204 struct pinmux_irq {
205 	const short *gpios;
206 };
207 
208 /*
209  * Describe the mapping from GPIOs to a single IRQ
210  *   - ids...: List of GPIOs that are mapped to the same IRQ
211  */
212 #define PINMUX_IRQ(ids...) {						\
213 	.gpios = (const short []) { ids, -1 }				\
214 }
215 
216 struct pinmux_range {
217 	u16 begin;
218 	u16 end;
219 	u16 force;
220 };
221 
222 struct sh_pfc_window {
223 	phys_addr_t phys;
224 	void __iomem *virt;
225 	unsigned long size;
226 };
227 
228 struct sh_pfc_pin_range;
229 
230 struct sh_pfc {
231 	struct device *dev;
232 	const struct sh_pfc_soc_info *info;
233 	spinlock_t lock;
234 
235 	unsigned int num_windows;
236 	struct sh_pfc_window *windows;
237 	unsigned int num_irqs;
238 	unsigned int *irqs;
239 
240 	struct sh_pfc_pin_range *ranges;
241 	unsigned int nr_ranges;
242 
243 	unsigned int nr_gpio_pins;
244 
245 	struct sh_pfc_chip *gpio;
246 	u32 *saved_regs;
247 };
248 
249 struct sh_pfc_soc_operations {
250 	int (*init)(struct sh_pfc *pfc);
251 	unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
252 	void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
253 			 unsigned int bias);
254 	int (*pin_to_pocctrl)(unsigned int pin, u32 *pocctrl);
255 	int (*pin_to_portcr)(unsigned int pin);
256 };
257 
258 struct sh_pfc_soc_info {
259 	const char *name;
260 	const struct sh_pfc_soc_operations *ops;
261 
262 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO
263 	struct pinmux_range input;
264 	struct pinmux_range output;
265 	const struct pinmux_irq *gpio_irq;
266 	unsigned int gpio_irq_size;
267 #endif
268 
269 	struct pinmux_range function;
270 
271 	const struct sh_pfc_pin *pins;
272 	unsigned int nr_pins;
273 	const struct sh_pfc_pin_group *groups;
274 	unsigned int nr_groups;
275 	const struct sh_pfc_function *functions;
276 	unsigned int nr_functions;
277 
278 #ifdef CONFIG_PINCTRL_SH_FUNC_GPIO
279 	const struct pinmux_func *func_gpios;
280 	unsigned int nr_func_gpios;
281 #endif
282 
283 	const struct pinmux_cfg_reg *cfg_regs;
284 	const struct pinmux_drive_reg *drive_regs;
285 	const struct pinmux_bias_reg *bias_regs;
286 	const struct pinmux_ioctrl_reg *ioctrl_regs;
287 	const struct pinmux_data_reg *data_regs;
288 
289 	const u16 *pinmux_data;
290 	unsigned int pinmux_data_size;
291 
292 	u32 unlock_reg;		/* can be literal address or mask */
293 };
294 
295 extern const struct sh_pfc_soc_info emev2_pinmux_info;
296 extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
297 extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
298 extern const struct sh_pfc_soc_info r8a7742_pinmux_info;
299 extern const struct sh_pfc_soc_info r8a7743_pinmux_info;
300 extern const struct sh_pfc_soc_info r8a7744_pinmux_info;
301 extern const struct sh_pfc_soc_info r8a7745_pinmux_info;
302 extern const struct sh_pfc_soc_info r8a77470_pinmux_info;
303 extern const struct sh_pfc_soc_info r8a774a1_pinmux_info;
304 extern const struct sh_pfc_soc_info r8a774b1_pinmux_info;
305 extern const struct sh_pfc_soc_info r8a774c0_pinmux_info;
306 extern const struct sh_pfc_soc_info r8a774e1_pinmux_info;
307 extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
308 extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
309 extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
310 extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
311 extern const struct sh_pfc_soc_info r8a7792_pinmux_info;
312 extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
313 extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
314 extern const struct sh_pfc_soc_info r8a77951_pinmux_info;
315 extern const struct sh_pfc_soc_info r8a77960_pinmux_info;
316 extern const struct sh_pfc_soc_info r8a77961_pinmux_info;
317 extern const struct sh_pfc_soc_info r8a77965_pinmux_info;
318 extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
319 extern const struct sh_pfc_soc_info r8a77980_pinmux_info;
320 extern const struct sh_pfc_soc_info r8a77990_pinmux_info;
321 extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
322 extern const struct sh_pfc_soc_info r8a779a0_pinmux_info;
323 extern const struct sh_pfc_soc_info r8a779f0_pinmux_info;
324 extern const struct sh_pfc_soc_info r8a779g0_pinmux_info;
325 extern const struct sh_pfc_soc_info sh7203_pinmux_info;
326 extern const struct sh_pfc_soc_info sh7264_pinmux_info;
327 extern const struct sh_pfc_soc_info sh7269_pinmux_info;
328 extern const struct sh_pfc_soc_info sh73a0_pinmux_info;
329 extern const struct sh_pfc_soc_info sh7720_pinmux_info;
330 extern const struct sh_pfc_soc_info sh7722_pinmux_info;
331 extern const struct sh_pfc_soc_info sh7723_pinmux_info;
332 extern const struct sh_pfc_soc_info sh7724_pinmux_info;
333 extern const struct sh_pfc_soc_info sh7734_pinmux_info;
334 extern const struct sh_pfc_soc_info sh7757_pinmux_info;
335 extern const struct sh_pfc_soc_info sh7785_pinmux_info;
336 extern const struct sh_pfc_soc_info sh7786_pinmux_info;
337 extern const struct sh_pfc_soc_info shx3_pinmux_info;
338 
339 /* -----------------------------------------------------------------------------
340  * Helper macros to create pin and port lists
341  */
342 
343 /*
344  * sh_pfc_soc_info pinmux_data array macros
345  */
346 
347 /*
348  * Describe generic pinmux data
349  *   - data_or_mark: *_DATA or *_MARK enum ID
350  *   - ids...: List of enum IDs to associate with data_or_mark
351  */
352 #define PINMUX_DATA(data_or_mark, ids...)	data_or_mark, ids, 0
353 
354 /*
355  * Describe a pinmux configuration without GPIO function that needs
356  * configuration in a Peripheral Function Select Register (IPSR)
357  *   - ipsr: IPSR field (unused, for documentation purposes only)
358  *   - fn: Function name, referring to a field in the IPSR
359  */
360 #define PINMUX_IPSR_NOGP(ipsr, fn)					\
361 	PINMUX_DATA(fn##_MARK, FN_##fn)
362 
363 /*
364  * Describe a pinmux configuration with GPIO function that needs configuration
365  * in both a Peripheral Function Select Register (IPSR) and in a
366  * GPIO/Peripheral Function Select Register (GPSR)
367  *   - ipsr: IPSR field
368  *   - fn: Function name, also referring to the IPSR field
369  */
370 #define PINMUX_IPSR_GPSR(ipsr, fn)					\
371 	PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
372 
373 /*
374  * Describe a pinmux configuration without GPIO function that needs
375  * configuration in a Peripheral Function Select Register (IPSR), and where the
376  * pinmux function has a representation in a Module Select Register (MOD_SEL).
377  *   - ipsr: IPSR field (unused, for documentation purposes only)
378  *   - fn: Function name, also referring to the IPSR field
379  *   - msel: Module selector
380  */
381 #define PINMUX_IPSR_NOGM(ipsr, fn, msel)				\
382 	PINMUX_DATA(fn##_MARK, FN_##fn, FN_##msel)
383 
384 /*
385  * Describe a pinmux configuration with GPIO function where the pinmux function
386  * has no representation in a Peripheral Function Select Register (IPSR), but
387  * instead solely depends on a group selection.
388  *   - gpsr: GPSR field
389  *   - fn: Function name, also referring to the GPSR field
390  *   - gsel: Group selector
391  */
392 #define PINMUX_IPSR_NOFN(gpsr, fn, gsel)				\
393 	PINMUX_DATA(fn##_MARK, FN_##gpsr, FN_##gsel)
394 
395 /*
396  * Describe a pinmux configuration with GPIO function that needs configuration
397  * in both a Peripheral Function Select Register (IPSR) and a GPIO/Peripheral
398  * Function Select Register (GPSR), and where the pinmux function has a
399  * representation in a Module Select Register (MOD_SEL).
400  *   - ipsr: IPSR field
401  *   - fn: Function name, also referring to the IPSR field
402  *   - msel: Module selector
403  */
404 #define PINMUX_IPSR_MSEL(ipsr, fn, msel)				\
405 	PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr)
406 
407 /*
408  * Describe a pinmux configuration similar to PINMUX_IPSR_MSEL, but with
409  * an additional select register that controls physical multiplexing
410  * with another pin.
411  *   - ipsr: IPSR field
412  *   - fn: Function name, also referring to the IPSR field
413  *   - psel: Physical multiplexing selector
414  *   - msel: Module selector
415  */
416 #define PINMUX_IPSR_PHYS_MSEL(ipsr, fn, psel, msel) \
417 	PINMUX_DATA(fn##_MARK, FN_##psel, FN_##msel, FN_##fn, FN_##ipsr)
418 
419 /*
420  * Describe a pinmux configuration in which a pin is physically multiplexed
421  * with other pins.
422  *   - ipsr: IPSR field
423  *   - fn: Function name
424  *   - psel: Physical multiplexing selector
425  */
426 #define PINMUX_IPSR_PHYS(ipsr, fn, psel) \
427 	PINMUX_DATA(fn##_MARK, FN_##psel, FN_##ipsr)
428 
429 /*
430  * Describe a pinmux configuration for a single-function pin with GPIO
431  * capability.
432  *   - fn: Function name
433  */
434 #define PINMUX_SINGLE(fn)						\
435 	PINMUX_DATA(fn##_MARK, FN_##fn)
436 
437 /*
438  * GP port style (32 ports banks)
439  */
440 
441 #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg)				\
442 	fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
443 #define PORT_GP_1(bank, pin, fn, sfx)	PORT_GP_CFG_1(bank, pin, fn, sfx, 0)
444 
445 #define PORT_GP_CFG_2(bank, fn, sfx, cfg)				\
446 	PORT_GP_CFG_1(bank, 0,  fn, sfx, cfg),				\
447 	PORT_GP_CFG_1(bank, 1,  fn, sfx, cfg)
448 #define PORT_GP_2(bank, fn, sfx)	PORT_GP_CFG_2(bank, fn, sfx, 0)
449 
450 #define PORT_GP_CFG_4(bank, fn, sfx, cfg)				\
451 	PORT_GP_CFG_2(bank, fn, sfx, cfg),				\
452 	PORT_GP_CFG_1(bank, 2,  fn, sfx, cfg),				\
453 	PORT_GP_CFG_1(bank, 3,  fn, sfx, cfg)
454 #define PORT_GP_4(bank, fn, sfx)	PORT_GP_CFG_4(bank, fn, sfx, 0)
455 
456 #define PORT_GP_CFG_6(bank, fn, sfx, cfg)				\
457 	PORT_GP_CFG_4(bank, fn, sfx, cfg),				\
458 	PORT_GP_CFG_1(bank, 4,  fn, sfx, cfg),				\
459 	PORT_GP_CFG_1(bank, 5,  fn, sfx, cfg)
460 #define PORT_GP_6(bank, fn, sfx)	PORT_GP_CFG_6(bank, fn, sfx, 0)
461 
462 #define PORT_GP_CFG_7(bank, fn, sfx, cfg)				\
463 	PORT_GP_CFG_6(bank, fn, sfx, cfg),				\
464 	PORT_GP_CFG_1(bank, 6,  fn, sfx, cfg)
465 #define PORT_GP_7(bank, fn, sfx)	PORT_GP_CFG_7(bank, fn, sfx, 0)
466 
467 #define PORT_GP_CFG_8(bank, fn, sfx, cfg)				\
468 	PORT_GP_CFG_7(bank, fn, sfx, cfg),				\
469 	PORT_GP_CFG_1(bank, 7,  fn, sfx, cfg)
470 #define PORT_GP_8(bank, fn, sfx)	PORT_GP_CFG_8(bank, fn, sfx, 0)
471 
472 #define PORT_GP_CFG_9(bank, fn, sfx, cfg)				\
473 	PORT_GP_CFG_8(bank, fn, sfx, cfg),				\
474 	PORT_GP_CFG_1(bank, 8,  fn, sfx, cfg)
475 #define PORT_GP_9(bank, fn, sfx)	PORT_GP_CFG_9(bank, fn, sfx, 0)
476 
477 #define PORT_GP_CFG_10(bank, fn, sfx, cfg)				\
478 	PORT_GP_CFG_9(bank, fn, sfx, cfg),				\
479 	PORT_GP_CFG_1(bank, 9,  fn, sfx, cfg)
480 #define PORT_GP_10(bank, fn, sfx)	PORT_GP_CFG_10(bank, fn, sfx, 0)
481 
482 #define PORT_GP_CFG_11(bank, fn, sfx, cfg)				\
483 	PORT_GP_CFG_10(bank, fn, sfx, cfg),				\
484 	PORT_GP_CFG_1(bank, 10, fn, sfx, cfg)
485 #define PORT_GP_11(bank, fn, sfx)	PORT_GP_CFG_11(bank, fn, sfx, 0)
486 
487 #define PORT_GP_CFG_12(bank, fn, sfx, cfg)				\
488 	PORT_GP_CFG_11(bank, fn, sfx, cfg),				\
489 	PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
490 #define PORT_GP_12(bank, fn, sfx)	PORT_GP_CFG_12(bank, fn, sfx, 0)
491 
492 #define PORT_GP_CFG_13(bank, fn, sfx, cfg)				\
493 	PORT_GP_CFG_12(bank, fn, sfx, cfg),				\
494 	PORT_GP_CFG_1(bank, 12, fn, sfx, cfg)
495 #define PORT_GP_13(bank, fn, sfx)	PORT_GP_CFG_13(bank, fn, sfx, 0)
496 
497 #define PORT_GP_CFG_14(bank, fn, sfx, cfg)				\
498 	PORT_GP_CFG_13(bank, fn, sfx, cfg),				\
499 	PORT_GP_CFG_1(bank, 13, fn, sfx, cfg)
500 #define PORT_GP_14(bank, fn, sfx)	PORT_GP_CFG_14(bank, fn, sfx, 0)
501 
502 #define PORT_GP_CFG_15(bank, fn, sfx, cfg)				\
503 	PORT_GP_CFG_14(bank, fn, sfx, cfg),				\
504 	PORT_GP_CFG_1(bank, 14, fn, sfx, cfg)
505 #define PORT_GP_15(bank, fn, sfx)	PORT_GP_CFG_15(bank, fn, sfx, 0)
506 
507 #define PORT_GP_CFG_16(bank, fn, sfx, cfg)				\
508 	PORT_GP_CFG_15(bank, fn, sfx, cfg),				\
509 	PORT_GP_CFG_1(bank, 15, fn, sfx, cfg)
510 #define PORT_GP_16(bank, fn, sfx)	PORT_GP_CFG_16(bank, fn, sfx, 0)
511 
512 #define PORT_GP_CFG_17(bank, fn, sfx, cfg)				\
513 	PORT_GP_CFG_16(bank, fn, sfx, cfg),				\
514 	PORT_GP_CFG_1(bank, 16, fn, sfx, cfg)
515 #define PORT_GP_17(bank, fn, sfx)	PORT_GP_CFG_17(bank, fn, sfx, 0)
516 
517 #define PORT_GP_CFG_18(bank, fn, sfx, cfg)				\
518 	PORT_GP_CFG_17(bank, fn, sfx, cfg),				\
519 	PORT_GP_CFG_1(bank, 17, fn, sfx, cfg)
520 #define PORT_GP_18(bank, fn, sfx)	PORT_GP_CFG_18(bank, fn, sfx, 0)
521 
522 #define PORT_GP_CFG_19(bank, fn, sfx, cfg)				\
523 	PORT_GP_CFG_18(bank, fn, sfx, cfg),				\
524 	PORT_GP_CFG_1(bank, 18, fn, sfx, cfg)
525 #define PORT_GP_19(bank, fn, sfx)	PORT_GP_CFG_19(bank, fn, sfx, 0)
526 
527 #define PORT_GP_CFG_20(bank, fn, sfx, cfg)				\
528 	PORT_GP_CFG_19(bank, fn, sfx, cfg),				\
529 	PORT_GP_CFG_1(bank, 19, fn, sfx, cfg)
530 #define PORT_GP_20(bank, fn, sfx)	PORT_GP_CFG_20(bank, fn, sfx, 0)
531 
532 #define PORT_GP_CFG_21(bank, fn, sfx, cfg)				\
533 	PORT_GP_CFG_20(bank, fn, sfx, cfg),				\
534 	PORT_GP_CFG_1(bank, 20, fn, sfx, cfg)
535 #define PORT_GP_21(bank, fn, sfx)	PORT_GP_CFG_21(bank, fn, sfx, 0)
536 
537 #define PORT_GP_CFG_22(bank, fn, sfx, cfg)				\
538 	PORT_GP_CFG_21(bank, fn, sfx, cfg),				\
539 	PORT_GP_CFG_1(bank, 21, fn, sfx, cfg)
540 #define PORT_GP_22(bank, fn, sfx)	PORT_GP_CFG_22(bank, fn, sfx, 0)
541 
542 #define PORT_GP_CFG_23(bank, fn, sfx, cfg)				\
543 	PORT_GP_CFG_22(bank, fn, sfx, cfg),				\
544 	PORT_GP_CFG_1(bank, 22, fn, sfx, cfg)
545 #define PORT_GP_23(bank, fn, sfx)	PORT_GP_CFG_23(bank, fn, sfx, 0)
546 
547 #define PORT_GP_CFG_24(bank, fn, sfx, cfg)				\
548 	PORT_GP_CFG_23(bank, fn, sfx, cfg),				\
549 	PORT_GP_CFG_1(bank, 23, fn, sfx, cfg)
550 #define PORT_GP_24(bank, fn, sfx)	PORT_GP_CFG_24(bank, fn, sfx, 0)
551 
552 #define PORT_GP_CFG_25(bank, fn, sfx, cfg)				\
553 	PORT_GP_CFG_24(bank, fn, sfx, cfg),				\
554 	PORT_GP_CFG_1(bank, 24, fn, sfx, cfg)
555 #define PORT_GP_25(bank, fn, sfx)	PORT_GP_CFG_25(bank, fn, sfx, 0)
556 
557 #define PORT_GP_CFG_26(bank, fn, sfx, cfg)				\
558 	PORT_GP_CFG_25(bank, fn, sfx, cfg),				\
559 	PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
560 #define PORT_GP_26(bank, fn, sfx)	PORT_GP_CFG_26(bank, fn, sfx, 0)
561 
562 #define PORT_GP_CFG_27(bank, fn, sfx, cfg)				\
563 	PORT_GP_CFG_26(bank, fn, sfx, cfg),				\
564 	PORT_GP_CFG_1(bank, 26, fn, sfx, cfg)
565 #define PORT_GP_27(bank, fn, sfx)	PORT_GP_CFG_27(bank, fn, sfx, 0)
566 
567 #define PORT_GP_CFG_28(bank, fn, sfx, cfg)				\
568 	PORT_GP_CFG_27(bank, fn, sfx, cfg),				\
569 	PORT_GP_CFG_1(bank, 27, fn, sfx, cfg)
570 #define PORT_GP_28(bank, fn, sfx)	PORT_GP_CFG_28(bank, fn, sfx, 0)
571 
572 #define PORT_GP_CFG_29(bank, fn, sfx, cfg)				\
573 	PORT_GP_CFG_28(bank, fn, sfx, cfg),				\
574 	PORT_GP_CFG_1(bank, 28, fn, sfx, cfg)
575 #define PORT_GP_29(bank, fn, sfx)	PORT_GP_CFG_29(bank, fn, sfx, 0)
576 
577 #define PORT_GP_CFG_30(bank, fn, sfx, cfg)				\
578 	PORT_GP_CFG_29(bank, fn, sfx, cfg),				\
579 	PORT_GP_CFG_1(bank, 29, fn, sfx, cfg)
580 #define PORT_GP_30(bank, fn, sfx)	PORT_GP_CFG_30(bank, fn, sfx, 0)
581 
582 #define PORT_GP_CFG_31(bank, fn, sfx, cfg)				\
583 	PORT_GP_CFG_30(bank, fn, sfx, cfg),				\
584 	PORT_GP_CFG_1(bank, 30, fn, sfx, cfg)
585 #define PORT_GP_31(bank, fn, sfx)	PORT_GP_CFG_31(bank, fn, sfx, 0)
586 
587 #define PORT_GP_CFG_32(bank, fn, sfx, cfg)				\
588 	PORT_GP_CFG_31(bank, fn, sfx, cfg),				\
589 	PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)
590 #define PORT_GP_32(bank, fn, sfx)	PORT_GP_CFG_32(bank, fn, sfx, 0)
591 
592 #define PORT_GP_32_REV(bank, fn, sfx)					\
593 	PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx),	\
594 	PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx),	\
595 	PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx),	\
596 	PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx),	\
597 	PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx),	\
598 	PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx),	\
599 	PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx),	\
600 	PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx),	\
601 	PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx),	\
602 	PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx),	\
603 	PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx),	\
604 	PORT_GP_1(bank, 9,  fn, sfx), PORT_GP_1(bank, 8,  fn, sfx),	\
605 	PORT_GP_1(bank, 7,  fn, sfx), PORT_GP_1(bank, 6,  fn, sfx),	\
606 	PORT_GP_1(bank, 5,  fn, sfx), PORT_GP_1(bank, 4,  fn, sfx),	\
607 	PORT_GP_1(bank, 3,  fn, sfx), PORT_GP_1(bank, 2,  fn, sfx),	\
608 	PORT_GP_1(bank, 1,  fn, sfx), PORT_GP_1(bank, 0,  fn, sfx)
609 
610 /* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */
611 #define _GP_ALL(bank, pin, name, sfx, cfg)	name##_##sfx
612 #define GP_ALL(str)			CPU_ALL_GP(_GP_ALL, str)
613 
614 /* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */
615 #define _GP_GPIO(bank, _pin, _name, sfx, cfg) {				\
616 	.pin = (bank * 32) + _pin,					\
617 	.name = __stringify(_name),					\
618 	.enum_id = _name##_DATA,					\
619 	.configs = cfg,							\
620 }
621 #define PINMUX_GPIO_GP_ALL()		CPU_ALL_GP(_GP_GPIO, unused)
622 
623 /* PINMUX_DATA_GP_ALL -  Expand to a list of name_DATA, name_FN marks */
624 #define _GP_DATA(bank, pin, name, sfx, cfg)	PINMUX_DATA(name##_DATA, name##_FN)
625 #define PINMUX_DATA_GP_ALL()		CPU_ALL_GP(_GP_DATA, unused)
626 
627 /*
628  * GP_ASSIGN_LAST() - Expand to an enum definition for the last GP pin
629  *
630  * The largest GP pin index is obtained by taking the size of a union,
631  * containing one array per GP pin, sized by the corresponding pin index.
632  * As the fields in the CPU_ALL_GP() macro definition are separated by commas,
633  * while the members of a union must be terminated by semicolons, the commas
634  * are absorbed by wrapping them inside dummy attributes.
635  */
636 #define _GP_ENTRY(bank, pin, name, sfx, cfg)				\
637 	deprecated)); char name[(bank * 32) + pin] __attribute__((deprecated
638 #define GP_ASSIGN_LAST()						\
639 	GP_LAST = sizeof(union {					\
640 		char dummy[0] __attribute__((deprecated,		\
641 		CPU_ALL_GP(_GP_ENTRY, unused),				\
642 		deprecated));						\
643 	})
644 
645 /*
646  * PORT style (linear pin space)
647  */
648 
649 #define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx)
650 
651 #define PORT_10(pn, fn, pfx, sfx)					  \
652 	PORT_1(pn,   fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx),	  \
653 	PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx),	  \
654 	PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx),	  \
655 	PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx),	  \
656 	PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx)
657 
658 #define PORT_90(pn, fn, pfx, sfx)					  \
659 	PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \
660 	PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \
661 	PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \
662 	PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \
663 	PORT_10(pn+90, fn, pfx##9, sfx)
664 
665 /* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */
666 #define _PORT_ALL(pn, pfx, sfx)		pfx##_##sfx
667 #define PORT_ALL(str)			CPU_ALL_PORT(_PORT_ALL, PORT, str)
668 
669 /* PINMUX_GPIO - Expand to a sh_pfc_pin entry */
670 #define PINMUX_GPIO(_pin)						\
671 	[GPIO_##_pin] = {						\
672 		.pin = (u16)-1,						\
673 		.name = __stringify(GPIO_##_pin),			\
674 		.enum_id = _pin##_DATA,					\
675 	}
676 
677 /* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */
678 #define SH_PFC_PIN_CFG(_pin, cfgs) {					\
679 	.pin = _pin,							\
680 	.name = __stringify(PORT##_pin),				\
681 	.enum_id = PORT##_pin##_DATA,					\
682 	.configs = cfgs,						\
683 }
684 
685 /* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0,
686  *		     PORT_name_OUT, PORT_name_IN marks
687  */
688 #define _PORT_DATA(pn, pfx, sfx)					\
689 	PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0,			\
690 		    PORT##pfx##_OUT, PORT##pfx##_IN)
691 #define PINMUX_DATA_ALL()		CPU_ALL_PORT(_PORT_DATA, , unused)
692 
693 /*
694  * PORT_ASSIGN_LAST() - Expand to an enum definition for the last PORT pin
695  *
696  * The largest PORT pin index is obtained by taking the size of a union,
697  * containing one array per PORT pin, sized by the corresponding pin index.
698  * As the fields in the CPU_ALL_PORT() macro definition are separated by
699  * commas, while the members of a union must be terminated by semicolons, the
700  * commas are absorbed by wrapping them inside dummy attributes.
701  */
702 #define _PORT_ENTRY(pn, pfx, sfx)					\
703 	deprecated)); char pfx[pn] __attribute__((deprecated
704 #define PORT_ASSIGN_LAST()						\
705 	PORT_LAST = sizeof(union {					\
706 		char dummy[0] __attribute__((deprecated,		\
707 		CPU_ALL_PORT(_PORT_ENTRY, PORT, unused),		\
708 		deprecated));						\
709 	})
710 
711 /* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */
712 #define PINMUX_GPIO_FN(gpio, base, data_or_mark)			\
713 	[gpio - (base)] = {						\
714 		.name = __stringify(gpio),				\
715 		.enum_id = data_or_mark,				\
716 	}
717 #define GPIO_FN(str)							\
718 	PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
719 
720 /*
721  * Pins not associated with a GPIO port
722  */
723 
724 #define PIN_NOGP_CFG(pin, name, fn, cfg)	fn(pin, name, cfg)
725 #define PIN_NOGP(pin, name, fn)			fn(pin, name, 0)
726 
727 /* NOGP_ALL - Expand to a list of PIN_id */
728 #define _NOGP_ALL(pin, name, cfg)		PIN_##pin
729 #define NOGP_ALL()				CPU_ALL_NOGP(_NOGP_ALL)
730 
731 /* PINMUX_NOGP_ALL - Expand to a list of sh_pfc_pin entries */
732 #define _NOGP_PINMUX(_pin, _name, cfg) {				\
733 	.pin = PIN_##_pin,						\
734 	.name = "PIN_" _name,						\
735 	.configs = SH_PFC_PIN_CFG_NO_GPIO | cfg,			\
736 }
737 #define PINMUX_NOGP_ALL()		CPU_ALL_NOGP(_NOGP_PINMUX)
738 
739 /*
740  * PORTnCR helper macro for SH-Mobile/R-Mobile
741  */
742 #define PORTCR(nr, reg) {						\
743 	PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, GROUP(-2, 2, -1, 3),	\
744 			   GROUP(					\
745 		/* PULMD[1:0], handled by .set_bias() */		\
746 		/* IE and OE */						\
747 		0, PORT##nr##_OUT, PORT##nr##_IN, 0,			\
748 		/* SEC, not supported */				\
749 		/* PTMD[2:0] */						\
750 		PORT##nr##_FN0, PORT##nr##_FN1,				\
751 		PORT##nr##_FN2, PORT##nr##_FN3,				\
752 		PORT##nr##_FN4, PORT##nr##_FN5,				\
753 		PORT##nr##_FN6, PORT##nr##_FN7				\
754 	))								\
755 }
756 
757 /*
758  * GPIO number helper macro for R-Car
759  */
760 #define RCAR_GP_PIN(bank, pin)		(((bank) * 32) + (pin))
761 
762 /*
763  * Bias helpers
764  */
765 const struct pinmux_bias_reg *
766 rcar_pin_to_bias_reg(const struct sh_pfc_soc_info *info, unsigned int pin,
767 		     unsigned int *bit);
768 unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin);
769 void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
770 			  unsigned int bias);
771 
772 unsigned int rmobile_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin);
773 void rmobile_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
774 			     unsigned int bias);
775 
776 #endif /* __SH_PFC_H */
777