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Searched refs:PMCNTENSET (Results 1 – 3 of 3) sorted by relevance

/openbmc/linux/drivers/perf/
H A Dqcom_l3_pmu.c91 #define PMCNTENSET(__cntr) (1UL << ((__cntr) & 0x7)) macro
219 writel_relaxed(PMCNTENSET(idx + 1), l3pmu->regs + L3_M_BC_CNTENSET); in qcom_l3_cache__64bit_counter_start()
221 writel_relaxed(PMCNTENSET(idx), l3pmu->regs + L3_M_BC_CNTENSET); in qcom_l3_cache__64bit_counter_start()
296 writel_relaxed(PMCNTENSET(idx), l3pmu->regs + L3_M_BC_CNTENSET); in qcom_l3_cache__32bit_counter_start()
/openbmc/linux/arch/arm/include/asm/
H A Darm_pmuv3.h15 #define PMCNTENSET __ACCESS_CP15(c9, 0, c12, 1) macro
157 write_sysreg(val, PMCNTENSET); in write_pmcntenset()
/openbmc/linux/drivers/perf/arm_cspmu/
H A Darm_cspmu.c50 #define PMCNTENSET 0xC00 macro
752 cnten_off = PMCNTENSET + (4 * reg_id); in arm_cspmu_enable_counter()