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Searched refs:PLL_PPLL (Results 1 – 14 of 14) sorted by relevance

/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3566-anbernic-rg353x.dtsi20 <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
H A Drk3566-anbernic-rg503.dts109 <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
H A Drk356x.dtsi425 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
H A Drk3588s.dtsi533 <&cru PLL_PPLL>, <&cru PLL_AUPLL>,
H A Drk3399.dtsi1492 assigned-clocks = <&pmucru PLL_PPLL>;
/openbmc/u-boot/include/dt-bindings/clock/
H A Drk3399-cru.h340 #define PLL_PPLL 1 macro
/openbmc/linux/include/dt-bindings/clock/
H A Drk3399-cru.h342 #define PLL_PPLL 1 macro
H A Drockchip,rk3588-cru.h23 #define PLL_PPLL 8 macro
H A Drk3568-cru.h13 #define PLL_PPLL 1 macro
/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rk3399.c1319 case PLL_PPLL: in rk3399_pmuclk_get_rate()
1342 case PLL_PPLL: in rk3399_pmuclk_set_rate()
/openbmc/linux/drivers/clk/rockchip/
H A Dclk-rk3399.c236 [ppll] = PLL(pll_rk3399, PLL_PPLL, "ppll", mux_pll_p, 0, RK3399_PMU_PLL_CON(0),
H A Dclk-rk3568.c314 [ppll] = PLL(pll_rk3328, PLL_PPLL, "ppll", mux_pll_p,
H A Dclk-rk3588.c692 [ppll] = PLL(pll_rk3588_core, PLL_PPLL, "ppll", mux_pll_p,
/openbmc/u-boot/arch/arm/dts/
H A Drk3399.dtsi1277 assigned-clocks = <&pmucru PLL_PPLL>;