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Searched refs:PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK__SHIFT (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h8396 #define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK__SHIFT 0x00000007 macro
H A Ddce_8_0_sh_mask.h2038 #define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK__SHIFT 0x7 macro
H A Ddce_10_0_sh_mask.h11590 #define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK__SHIFT 0x7 macro
H A Ddce_11_0_sh_mask.h11402 #define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK__SHIFT 0x7 macro