xref: /openbmc/linux/drivers/clk/qcom/clk-alpha-pll.c (revision 360823a09426347ea8f232b0b0b5156d0aed0302)
1  // SPDX-License-Identifier: GPL-2.0
2  /*
3   * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.
4   * Copyright (c) 2021, 2023, Qualcomm Innovation Center, Inc. All rights reserved.
5   */
6  
7  #include <linux/kernel.h>
8  #include <linux/export.h>
9  #include <linux/clk-provider.h>
10  #include <linux/regmap.h>
11  #include <linux/delay.h>
12  
13  #include "clk-alpha-pll.h"
14  #include "common.h"
15  
16  #define PLL_MODE(p)		((p)->offset + 0x0)
17  # define PLL_OUTCTRL		BIT(0)
18  # define PLL_BYPASSNL		BIT(1)
19  # define PLL_RESET_N		BIT(2)
20  # define PLL_OFFLINE_REQ	BIT(7)
21  # define PLL_LOCK_COUNT_SHIFT	8
22  # define PLL_LOCK_COUNT_MASK	0x3f
23  # define PLL_BIAS_COUNT_SHIFT	14
24  # define PLL_BIAS_COUNT_MASK	0x3f
25  # define PLL_VOTE_FSM_ENA	BIT(20)
26  # define PLL_FSM_ENA		BIT(20)
27  # define PLL_VOTE_FSM_RESET	BIT(21)
28  # define PLL_UPDATE		BIT(22)
29  # define PLL_UPDATE_BYPASS	BIT(23)
30  # define PLL_FSM_LEGACY_MODE	BIT(24)
31  # define PLL_OFFLINE_ACK	BIT(28)
32  # define ALPHA_PLL_ACK_LATCH	BIT(29)
33  # define PLL_ACTIVE_FLAG	BIT(30)
34  # define PLL_LOCK_DET		BIT(31)
35  
36  #define PLL_L_VAL(p)		((p)->offset + (p)->regs[PLL_OFF_L_VAL])
37  #define PLL_CAL_L_VAL(p)	((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL])
38  #define PLL_ALPHA_VAL(p)	((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
39  #define PLL_ALPHA_VAL_U(p)	((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])
40  
41  #define PLL_USER_CTL(p)		((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
42  # define PLL_POST_DIV_SHIFT	8
43  # define PLL_POST_DIV_MASK(p)	GENMASK((p)->width - 1, 0)
44  # define PLL_ALPHA_EN		BIT(24)
45  # define PLL_ALPHA_MODE		BIT(25)
46  # define PLL_VCO_SHIFT		20
47  # define PLL_VCO_MASK		0x3
48  
49  #define PLL_USER_CTL_U(p)	((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U])
50  #define PLL_USER_CTL_U1(p)	((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U1])
51  
52  #define PLL_CONFIG_CTL(p)	((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL])
53  #define PLL_CONFIG_CTL_U(p)	((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U])
54  #define PLL_CONFIG_CTL_U1(p)	((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1])
55  #define PLL_CONFIG_CTL_U2(p)	((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U2])
56  #define PLL_TEST_CTL(p)		((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
57  #define PLL_TEST_CTL_U(p)	((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
58  #define PLL_TEST_CTL_U1(p)     ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1])
59  #define PLL_TEST_CTL_U2(p)     ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U2])
60  #define PLL_STATUS(p)		((p)->offset + (p)->regs[PLL_OFF_STATUS])
61  #define PLL_OPMODE(p)		((p)->offset + (p)->regs[PLL_OFF_OPMODE])
62  #define PLL_FRAC(p)		((p)->offset + (p)->regs[PLL_OFF_FRAC])
63  
64  const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
65  	[CLK_ALPHA_PLL_TYPE_DEFAULT] =  {
66  		[PLL_OFF_L_VAL] = 0x04,
67  		[PLL_OFF_ALPHA_VAL] = 0x08,
68  		[PLL_OFF_ALPHA_VAL_U] = 0x0c,
69  		[PLL_OFF_USER_CTL] = 0x10,
70  		[PLL_OFF_USER_CTL_U] = 0x14,
71  		[PLL_OFF_CONFIG_CTL] = 0x18,
72  		[PLL_OFF_TEST_CTL] = 0x1c,
73  		[PLL_OFF_TEST_CTL_U] = 0x20,
74  		[PLL_OFF_STATUS] = 0x24,
75  	},
76  	[CLK_ALPHA_PLL_TYPE_HUAYRA] =  {
77  		[PLL_OFF_L_VAL] = 0x04,
78  		[PLL_OFF_ALPHA_VAL] = 0x08,
79  		[PLL_OFF_USER_CTL] = 0x10,
80  		[PLL_OFF_CONFIG_CTL] = 0x14,
81  		[PLL_OFF_CONFIG_CTL_U] = 0x18,
82  		[PLL_OFF_TEST_CTL] = 0x1c,
83  		[PLL_OFF_TEST_CTL_U] = 0x20,
84  		[PLL_OFF_STATUS] = 0x24,
85  	},
86  	[CLK_ALPHA_PLL_TYPE_BRAMMO] =  {
87  		[PLL_OFF_L_VAL] = 0x04,
88  		[PLL_OFF_ALPHA_VAL] = 0x08,
89  		[PLL_OFF_ALPHA_VAL_U] = 0x0c,
90  		[PLL_OFF_USER_CTL] = 0x10,
91  		[PLL_OFF_CONFIG_CTL] = 0x18,
92  		[PLL_OFF_TEST_CTL] = 0x1c,
93  		[PLL_OFF_STATUS] = 0x24,
94  	},
95  	[CLK_ALPHA_PLL_TYPE_FABIA] =  {
96  		[PLL_OFF_L_VAL] = 0x04,
97  		[PLL_OFF_USER_CTL] = 0x0c,
98  		[PLL_OFF_USER_CTL_U] = 0x10,
99  		[PLL_OFF_CONFIG_CTL] = 0x14,
100  		[PLL_OFF_CONFIG_CTL_U] = 0x18,
101  		[PLL_OFF_TEST_CTL] = 0x1c,
102  		[PLL_OFF_TEST_CTL_U] = 0x20,
103  		[PLL_OFF_STATUS] = 0x24,
104  		[PLL_OFF_OPMODE] = 0x2c,
105  		[PLL_OFF_FRAC] = 0x38,
106  	},
107  	[CLK_ALPHA_PLL_TYPE_TRION] = {
108  		[PLL_OFF_L_VAL] = 0x04,
109  		[PLL_OFF_CAL_L_VAL] = 0x08,
110  		[PLL_OFF_USER_CTL] = 0x0c,
111  		[PLL_OFF_USER_CTL_U] = 0x10,
112  		[PLL_OFF_USER_CTL_U1] = 0x14,
113  		[PLL_OFF_CONFIG_CTL] = 0x18,
114  		[PLL_OFF_CONFIG_CTL_U] = 0x1c,
115  		[PLL_OFF_CONFIG_CTL_U1] = 0x20,
116  		[PLL_OFF_TEST_CTL] = 0x24,
117  		[PLL_OFF_TEST_CTL_U] = 0x28,
118  		[PLL_OFF_TEST_CTL_U1] = 0x2c,
119  		[PLL_OFF_STATUS] = 0x30,
120  		[PLL_OFF_OPMODE] = 0x38,
121  		[PLL_OFF_ALPHA_VAL] = 0x40,
122  	},
123  	[CLK_ALPHA_PLL_TYPE_AGERA] =  {
124  		[PLL_OFF_L_VAL] = 0x04,
125  		[PLL_OFF_ALPHA_VAL] = 0x08,
126  		[PLL_OFF_USER_CTL] = 0x0c,
127  		[PLL_OFF_CONFIG_CTL] = 0x10,
128  		[PLL_OFF_CONFIG_CTL_U] = 0x14,
129  		[PLL_OFF_TEST_CTL] = 0x18,
130  		[PLL_OFF_TEST_CTL_U] = 0x1c,
131  		[PLL_OFF_STATUS] = 0x2c,
132  	},
133  	[CLK_ALPHA_PLL_TYPE_ZONDA] =  {
134  		[PLL_OFF_L_VAL] = 0x04,
135  		[PLL_OFF_ALPHA_VAL] = 0x08,
136  		[PLL_OFF_USER_CTL] = 0x0c,
137  		[PLL_OFF_CONFIG_CTL] = 0x10,
138  		[PLL_OFF_CONFIG_CTL_U] = 0x14,
139  		[PLL_OFF_CONFIG_CTL_U1] = 0x18,
140  		[PLL_OFF_TEST_CTL] = 0x1c,
141  		[PLL_OFF_TEST_CTL_U] = 0x20,
142  		[PLL_OFF_TEST_CTL_U1] = 0x24,
143  		[PLL_OFF_OPMODE] = 0x28,
144  		[PLL_OFF_STATUS] = 0x38,
145  	},
146  	[CLK_ALPHA_PLL_TYPE_LUCID_EVO] = {
147  		[PLL_OFF_OPMODE] = 0x04,
148  		[PLL_OFF_STATUS] = 0x0c,
149  		[PLL_OFF_L_VAL] = 0x10,
150  		[PLL_OFF_ALPHA_VAL] = 0x14,
151  		[PLL_OFF_USER_CTL] = 0x18,
152  		[PLL_OFF_USER_CTL_U] = 0x1c,
153  		[PLL_OFF_CONFIG_CTL] = 0x20,
154  		[PLL_OFF_CONFIG_CTL_U] = 0x24,
155  		[PLL_OFF_CONFIG_CTL_U1] = 0x28,
156  		[PLL_OFF_TEST_CTL] = 0x2c,
157  		[PLL_OFF_TEST_CTL_U] = 0x30,
158  		[PLL_OFF_TEST_CTL_U1] = 0x34,
159  	},
160  	[CLK_ALPHA_PLL_TYPE_LUCID_OLE] = {
161  		[PLL_OFF_OPMODE] = 0x04,
162  		[PLL_OFF_STATE] = 0x08,
163  		[PLL_OFF_STATUS] = 0x0c,
164  		[PLL_OFF_L_VAL] = 0x10,
165  		[PLL_OFF_ALPHA_VAL] = 0x14,
166  		[PLL_OFF_USER_CTL] = 0x18,
167  		[PLL_OFF_USER_CTL_U] = 0x1c,
168  		[PLL_OFF_CONFIG_CTL] = 0x20,
169  		[PLL_OFF_CONFIG_CTL_U] = 0x24,
170  		[PLL_OFF_CONFIG_CTL_U1] = 0x28,
171  		[PLL_OFF_TEST_CTL] = 0x2c,
172  		[PLL_OFF_TEST_CTL_U] = 0x30,
173  		[PLL_OFF_TEST_CTL_U1] = 0x34,
174  		[PLL_OFF_TEST_CTL_U2] = 0x38,
175  	},
176  	[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO] = {
177  		[PLL_OFF_OPMODE] = 0x04,
178  		[PLL_OFF_STATUS] = 0x0c,
179  		[PLL_OFF_L_VAL] = 0x10,
180  		[PLL_OFF_USER_CTL] = 0x14,
181  		[PLL_OFF_USER_CTL_U] = 0x18,
182  		[PLL_OFF_CONFIG_CTL] = 0x1c,
183  		[PLL_OFF_CONFIG_CTL_U] = 0x20,
184  		[PLL_OFF_CONFIG_CTL_U1] = 0x24,
185  		[PLL_OFF_TEST_CTL] = 0x28,
186  		[PLL_OFF_TEST_CTL_U] = 0x2c,
187  	},
188  	[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO] =  {
189  		[PLL_OFF_L_VAL] = 0x04,
190  		[PLL_OFF_ALPHA_VAL] = 0x08,
191  		[PLL_OFF_ALPHA_VAL_U] = 0x0c,
192  		[PLL_OFF_TEST_CTL] = 0x10,
193  		[PLL_OFF_TEST_CTL_U] = 0x14,
194  		[PLL_OFF_USER_CTL] = 0x18,
195  		[PLL_OFF_USER_CTL_U] = 0x1c,
196  		[PLL_OFF_CONFIG_CTL] = 0x20,
197  		[PLL_OFF_STATUS] = 0x24,
198  	},
199  	[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO] =  {
200  		[PLL_OFF_L_VAL] = 0x04,
201  		[PLL_OFF_ALPHA_VAL] = 0x08,
202  		[PLL_OFF_ALPHA_VAL_U] = 0x0c,
203  		[PLL_OFF_TEST_CTL] = 0x10,
204  		[PLL_OFF_TEST_CTL_U] = 0x14,
205  		[PLL_OFF_USER_CTL] = 0x18,
206  		[PLL_OFF_CONFIG_CTL] = 0x1C,
207  		[PLL_OFF_STATUS] = 0x20,
208  	},
209  	[CLK_ALPHA_PLL_TYPE_STROMER] = {
210  		[PLL_OFF_L_VAL] = 0x08,
211  		[PLL_OFF_ALPHA_VAL] = 0x10,
212  		[PLL_OFF_ALPHA_VAL_U] = 0x14,
213  		[PLL_OFF_USER_CTL] = 0x18,
214  		[PLL_OFF_USER_CTL_U] = 0x1c,
215  		[PLL_OFF_CONFIG_CTL] = 0x20,
216  		[PLL_OFF_TEST_CTL] = 0x30,
217  		[PLL_OFF_TEST_CTL_U] = 0x34,
218  		[PLL_OFF_STATUS] = 0x28,
219  	},
220  	[CLK_ALPHA_PLL_TYPE_STROMER_PLUS] =  {
221  		[PLL_OFF_L_VAL] = 0x04,
222  		[PLL_OFF_USER_CTL] = 0x08,
223  		[PLL_OFF_USER_CTL_U] = 0x0c,
224  		[PLL_OFF_CONFIG_CTL] = 0x10,
225  		[PLL_OFF_TEST_CTL] = 0x14,
226  		[PLL_OFF_TEST_CTL_U] = 0x18,
227  		[PLL_OFF_STATUS] = 0x1c,
228  		[PLL_OFF_ALPHA_VAL] = 0x24,
229  		[PLL_OFF_ALPHA_VAL_U] = 0x28,
230  	},
231  	[CLK_ALPHA_PLL_TYPE_ZONDA_OLE] =  {
232  		[PLL_OFF_L_VAL] = 0x04,
233  		[PLL_OFF_ALPHA_VAL] = 0x08,
234  		[PLL_OFF_USER_CTL] = 0x0c,
235  		[PLL_OFF_USER_CTL_U] = 0x10,
236  		[PLL_OFF_CONFIG_CTL] = 0x14,
237  		[PLL_OFF_CONFIG_CTL_U] = 0x18,
238  		[PLL_OFF_CONFIG_CTL_U1] = 0x1c,
239  		[PLL_OFF_CONFIG_CTL_U2] = 0x20,
240  		[PLL_OFF_TEST_CTL] = 0x24,
241  		[PLL_OFF_TEST_CTL_U] = 0x28,
242  		[PLL_OFF_TEST_CTL_U1] = 0x2c,
243  		[PLL_OFF_OPMODE] = 0x30,
244  		[PLL_OFF_STATUS] = 0x3c,
245  	},
246  	[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA] =  {
247  		[PLL_OFF_L_VAL] = 0x04,
248  		[PLL_OFF_ALPHA_VAL] = 0x08,
249  		[PLL_OFF_TEST_CTL] = 0x0c,
250  		[PLL_OFF_TEST_CTL_U] = 0x10,
251  		[PLL_OFF_USER_CTL] = 0x14,
252  		[PLL_OFF_CONFIG_CTL] = 0x18,
253  		[PLL_OFF_CONFIG_CTL_U] = 0x1c,
254  		[PLL_OFF_STATUS] = 0x20,
255  	},
256  
257  };
258  EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
259  
260  /*
261   * Even though 40 bits are present, use only 32 for ease of calculation.
262   */
263  #define ALPHA_REG_BITWIDTH	40
264  #define ALPHA_REG_16BIT_WIDTH	16
265  #define ALPHA_BITWIDTH		32U
266  #define ALPHA_SHIFT(w)		min(w, ALPHA_BITWIDTH)
267  
268  #define	ALPHA_PLL_STATUS_REG_SHIFT	8
269  
270  #define PLL_HUAYRA_M_WIDTH		8
271  #define PLL_HUAYRA_M_SHIFT		8
272  #define PLL_HUAYRA_M_MASK		0xff
273  #define PLL_HUAYRA_N_SHIFT		0
274  #define PLL_HUAYRA_N_MASK		0xff
275  #define PLL_HUAYRA_ALPHA_WIDTH		16
276  
277  #define PLL_STANDBY		0x0
278  #define PLL_RUN			0x1
279  #define PLL_OUT_MASK		0x7
280  #define PLL_RATE_MARGIN		500
281  
282  /* TRION PLL specific settings and offsets */
283  #define TRION_PLL_CAL_VAL	0x44
284  #define TRION_PCAL_DONE		BIT(26)
285  
286  /* LUCID PLL specific settings and offsets */
287  #define LUCID_PCAL_DONE		BIT(27)
288  
289  /* LUCID 5LPE PLL specific settings and offsets */
290  #define LUCID_5LPE_PCAL_DONE		BIT(11)
291  #define LUCID_5LPE_ALPHA_PLL_ACK_LATCH	BIT(13)
292  #define LUCID_5LPE_PLL_LATCH_INPUT	BIT(14)
293  #define LUCID_5LPE_ENABLE_VOTE_RUN	BIT(21)
294  
295  /* LUCID EVO PLL specific settings and offsets */
296  #define LUCID_EVO_PCAL_NOT_DONE		BIT(8)
297  #define LUCID_EVO_ENABLE_VOTE_RUN       BIT(25)
298  #define LUCID_EVO_PLL_L_VAL_MASK        GENMASK(15, 0)
299  #define LUCID_EVO_PLL_CAL_L_VAL_SHIFT	16
300  
301  /* ZONDA PLL specific */
302  #define ZONDA_PLL_OUT_MASK	0xf
303  #define ZONDA_STAY_IN_CFA	BIT(16)
304  #define ZONDA_PLL_FREQ_LOCK_DET	BIT(29)
305  
306  #define pll_alpha_width(p)					\
307  		((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ?	\
308  				 ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
309  
310  #define pll_has_64bit_config(p)	((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4)
311  
312  #define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \
313  					   struct clk_alpha_pll, clkr)
314  
315  #define to_clk_alpha_pll_postdiv(_hw) container_of(to_clk_regmap(_hw), \
316  					   struct clk_alpha_pll_postdiv, clkr)
317  
wait_for_pll(struct clk_alpha_pll * pll,u32 mask,bool inverse,const char * action)318  static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
319  			const char *action)
320  {
321  	u32 val;
322  	int count;
323  	int ret;
324  	const char *name = clk_hw_get_name(&pll->clkr.hw);
325  
326  	ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
327  	if (ret)
328  		return ret;
329  
330  	for (count = 200; count > 0; count--) {
331  		ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
332  		if (ret)
333  			return ret;
334  		if (inverse && !(val & mask))
335  			return 0;
336  		else if ((val & mask) == mask)
337  			return 0;
338  
339  		udelay(1);
340  	}
341  
342  	WARN(1, "%s failed to %s!\n", name, action);
343  	return -ETIMEDOUT;
344  }
345  
346  #define wait_for_pll_enable_active(pll) \
347  	wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable")
348  
349  #define wait_for_pll_enable_lock(pll) \
350  	wait_for_pll(pll, PLL_LOCK_DET, 0, "enable")
351  
352  #define wait_for_zonda_pll_freq_lock(pll) \
353  	wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable")
354  
355  #define wait_for_pll_disable(pll) \
356  	wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable")
357  
358  #define wait_for_pll_offline(pll) \
359  	wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline")
360  
361  #define wait_for_pll_update(pll) \
362  	wait_for_pll(pll, PLL_UPDATE, 1, "update")
363  
364  #define wait_for_pll_update_ack_set(pll) \
365  	wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set")
366  
367  #define wait_for_pll_update_ack_clear(pll) \
368  	wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear")
369  
clk_alpha_pll_write_config(struct regmap * regmap,unsigned int reg,unsigned int val)370  static void clk_alpha_pll_write_config(struct regmap *regmap, unsigned int reg,
371  					unsigned int val)
372  {
373  	if (val)
374  		regmap_write(regmap, reg, val);
375  }
376  
clk_alpha_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)377  void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
378  			     const struct alpha_pll_config *config)
379  {
380  	u32 val, mask;
381  
382  	regmap_write(regmap, PLL_L_VAL(pll), config->l);
383  	regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
384  	regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
385  
386  	if (pll_has_64bit_config(pll))
387  		regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
388  			     config->config_ctl_hi_val);
389  
390  	if (pll_alpha_width(pll) > 32)
391  		regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi);
392  
393  	val = config->main_output_mask;
394  	val |= config->aux_output_mask;
395  	val |= config->aux2_output_mask;
396  	val |= config->early_output_mask;
397  	val |= config->pre_div_val;
398  	val |= config->post_div_val;
399  	val |= config->vco_val;
400  	val |= config->alpha_en_mask;
401  	val |= config->alpha_mode_mask;
402  
403  	mask = config->main_output_mask;
404  	mask |= config->aux_output_mask;
405  	mask |= config->aux2_output_mask;
406  	mask |= config->early_output_mask;
407  	mask |= config->pre_div_mask;
408  	mask |= config->post_div_mask;
409  	mask |= config->vco_mask;
410  	mask |= config->alpha_en_mask;
411  	mask |= config->alpha_mode_mask;
412  
413  	regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
414  
415  	if (config->test_ctl_mask)
416  		regmap_update_bits(regmap, PLL_TEST_CTL(pll),
417  				   config->test_ctl_mask,
418  				   config->test_ctl_val);
419  	else
420  		clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
421  					   config->test_ctl_val);
422  
423  	if (config->test_ctl_hi_mask)
424  		regmap_update_bits(regmap, PLL_TEST_CTL_U(pll),
425  				   config->test_ctl_hi_mask,
426  				   config->test_ctl_hi_val);
427  	else
428  		clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
429  					   config->test_ctl_hi_val);
430  
431  	if (pll->flags & SUPPORTS_FSM_MODE)
432  		qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
433  }
434  EXPORT_SYMBOL_GPL(clk_alpha_pll_configure);
435  
clk_alpha_pll_hwfsm_enable(struct clk_hw * hw)436  static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
437  {
438  	int ret;
439  	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
440  	u32 val;
441  
442  	ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
443  	if (ret)
444  		return ret;
445  
446  	val |= PLL_FSM_ENA;
447  
448  	if (pll->flags & SUPPORTS_OFFLINE_REQ)
449  		val &= ~PLL_OFFLINE_REQ;
450  
451  	ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val);
452  	if (ret)
453  		return ret;
454  
455  	/* Make sure enable request goes through before waiting for update */
456  	mb();
457  
458  	return wait_for_pll_enable_active(pll);
459  }
460  
clk_alpha_pll_hwfsm_disable(struct clk_hw * hw)461  static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw)
462  {
463  	int ret;
464  	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
465  	u32 val;
466  
467  	ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
468  	if (ret)
469  		return;
470  
471  	if (pll->flags & SUPPORTS_OFFLINE_REQ) {
472  		ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
473  					 PLL_OFFLINE_REQ, PLL_OFFLINE_REQ);
474  		if (ret)
475  			return;
476  
477  		ret = wait_for_pll_offline(pll);
478  		if (ret)
479  			return;
480  	}
481  
482  	/* Disable hwfsm */
483  	ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
484  				 PLL_FSM_ENA, 0);
485  	if (ret)
486  		return;
487  
488  	wait_for_pll_disable(pll);
489  }
490  
pll_is_enabled(struct clk_hw * hw,u32 mask)491  static int pll_is_enabled(struct clk_hw *hw, u32 mask)
492  {
493  	int ret;
494  	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
495  	u32 val;
496  
497  	ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
498  	if (ret)
499  		return ret;
500  
501  	return !!(val & mask);
502  }
503  
clk_alpha_pll_hwfsm_is_enabled(struct clk_hw * hw)504  static int clk_alpha_pll_hwfsm_is_enabled(struct clk_hw *hw)
505  {
506  	return pll_is_enabled(hw, PLL_ACTIVE_FLAG);
507  }
508  
clk_alpha_pll_is_enabled(struct clk_hw * hw)509  static int clk_alpha_pll_is_enabled(struct clk_hw *hw)
510  {
511  	return pll_is_enabled(hw, PLL_LOCK_DET);
512  }
513  
clk_alpha_pll_enable(struct clk_hw * hw)514  static int clk_alpha_pll_enable(struct clk_hw *hw)
515  {
516  	int ret;
517  	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
518  	u32 val, mask;
519  
520  	mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
521  	ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
522  	if (ret)
523  		return ret;
524  
525  	/* If in FSM mode, just vote for it */
526  	if (val & PLL_VOTE_FSM_ENA) {
527  		ret = clk_enable_regmap(hw);
528  		if (ret)
529  			return ret;
530  		return wait_for_pll_enable_active(pll);
531  	}
532  
533  	/* Skip if already enabled */
534  	if ((val & mask) == mask)
535  		return 0;
536  
537  	ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
538  				 PLL_BYPASSNL, PLL_BYPASSNL);
539  	if (ret)
540  		return ret;
541  
542  	/*
543  	 * H/W requires a 5us delay between disabling the bypass and
544  	 * de-asserting the reset.
545  	 */
546  	mb();
547  	udelay(5);
548  
549  	ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
550  				 PLL_RESET_N, PLL_RESET_N);
551  	if (ret)
552  		return ret;
553  
554  	ret = wait_for_pll_enable_lock(pll);
555  	if (ret)
556  		return ret;
557  
558  	ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
559  				 PLL_OUTCTRL, PLL_OUTCTRL);
560  
561  	/* Ensure that the write above goes through before returning. */
562  	mb();
563  	return ret;
564  }
565  
clk_alpha_pll_disable(struct clk_hw * hw)566  static void clk_alpha_pll_disable(struct clk_hw *hw)
567  {
568  	int ret;
569  	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
570  	u32 val, mask;
571  
572  	ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
573  	if (ret)
574  		return;
575  
576  	/* If in FSM mode, just unvote it */
577  	if (val & PLL_VOTE_FSM_ENA) {
578  		clk_disable_regmap(hw);
579  		return;
580  	}
581  
582  	mask = PLL_OUTCTRL;
583  	regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
584  
585  	/* Delay of 2 output clock ticks required until output is disabled */
586  	mb();
587  	udelay(1);
588  
589  	mask = PLL_RESET_N | PLL_BYPASSNL;
590  	regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
591  }
592  
593  static unsigned long
alpha_pll_calc_rate(u64 prate,u32 l,u32 a,u32 alpha_width)594  alpha_pll_calc_rate(u64 prate, u32 l, u32 a, u32 alpha_width)
595  {
596  	return (prate * l) + ((prate * a) >> ALPHA_SHIFT(alpha_width));
597  }
598  
599  static unsigned long
alpha_pll_round_rate(unsigned long rate,unsigned long prate,u32 * l,u64 * a,u32 alpha_width)600  alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a,
601  		     u32 alpha_width)
602  {
603  	u64 remainder;
604  	u64 quotient;
605  
606  	quotient = rate;
607  	remainder = do_div(quotient, prate);
608  	*l = quotient;
609  
610  	if (!remainder) {
611  		*a = 0;
612  		return rate;
613  	}
614  
615  	/* Upper ALPHA_BITWIDTH bits of Alpha */
616  	quotient = remainder << ALPHA_SHIFT(alpha_width);
617  
618  	remainder = do_div(quotient, prate);
619  
620  	if (remainder)
621  		quotient++;
622  
623  	*a = quotient;
624  	return alpha_pll_calc_rate(prate, *l, *a, alpha_width);
625  }
626  
627  static const struct pll_vco *
alpha_pll_find_vco(const struct clk_alpha_pll * pll,unsigned long rate)628  alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate)
629  {
630  	const struct pll_vco *v = pll->vco_table;
631  	const struct pll_vco *end = v + pll->num_vco;
632  
633  	for (; v < end; v++)
634  		if (rate >= v->min_freq && rate <= v->max_freq)
635  			return v;
636  
637  	return NULL;
638  }
639  
640  static unsigned long
clk_alpha_pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)641  clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
642  {
643  	u32 l, low, high, ctl;
644  	u64 a = 0, prate = parent_rate;
645  	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
646  	u32 alpha_width = pll_alpha_width(pll);
647  
648  	regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
649  
650  	regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
651  	if (ctl & PLL_ALPHA_EN) {
652  		regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low);
653  		if (alpha_width > 32) {
654  			regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
655  				    &high);
656  			a = (u64)high << 32 | low;
657  		} else {
658  			a = low & GENMASK(alpha_width - 1, 0);
659  		}
660  
661  		if (alpha_width > ALPHA_BITWIDTH)
662  			a >>= alpha_width - ALPHA_BITWIDTH;
663  	}
664  
665  	return alpha_pll_calc_rate(prate, l, a, alpha_width);
666  }
667  
668  
__clk_alpha_pll_update_latch(struct clk_alpha_pll * pll)669  static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll)
670  {
671  	int ret;
672  	u32 mode;
673  
674  	regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode);
675  
676  	/* Latch the input to the PLL */
677  	regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE,
678  			   PLL_UPDATE);
679  
680  	/* Wait for 2 reference cycle before checking ACK bit */
681  	udelay(1);
682  
683  	/*
684  	 * PLL will latch the new L, Alpha and freq control word.
685  	 * PLL will respond by raising PLL_ACK_LATCH output when new programming
686  	 * has been latched in and PLL is being updated. When
687  	 * UPDATE_LOGIC_BYPASS bit is not set, PLL_UPDATE will be cleared
688  	 * automatically by hardware when PLL_ACK_LATCH is asserted by PLL.
689  	 */
690  	if (mode & PLL_UPDATE_BYPASS) {
691  		ret = wait_for_pll_update_ack_set(pll);
692  		if (ret)
693  			return ret;
694  
695  		regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0);
696  	} else {
697  		ret = wait_for_pll_update(pll);
698  		if (ret)
699  			return ret;
700  	}
701  
702  	ret = wait_for_pll_update_ack_clear(pll);
703  	if (ret)
704  		return ret;
705  
706  	/* Wait for PLL output to stabilize */
707  	udelay(10);
708  
709  	return 0;
710  }
711  
clk_alpha_pll_update_latch(struct clk_alpha_pll * pll,int (* is_enabled)(struct clk_hw *))712  static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll,
713  				      int (*is_enabled)(struct clk_hw *))
714  {
715  	if (!is_enabled(&pll->clkr.hw) ||
716  	    !(pll->flags & SUPPORTS_DYNAMIC_UPDATE))
717  		return 0;
718  
719  	return __clk_alpha_pll_update_latch(pll);
720  }
721  
__clk_alpha_pll_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate,int (* is_enabled)(struct clk_hw *))722  static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
723  				    unsigned long prate,
724  				    int (*is_enabled)(struct clk_hw *))
725  {
726  	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
727  	const struct pll_vco *vco;
728  	u32 l, alpha_width = pll_alpha_width(pll);
729  	u64 a;
730  
731  	rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
732  	vco = alpha_pll_find_vco(pll, rate);
733  	if (pll->vco_table && !vco) {
734  		pr_err("%s: alpha pll not in a valid vco range\n",
735  		       clk_hw_get_name(hw));
736  		return -EINVAL;
737  	}
738  
739  	regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
740  
741  	if (alpha_width > ALPHA_BITWIDTH)
742  		a <<= alpha_width - ALPHA_BITWIDTH;
743  
744  	if (alpha_width > 32)
745  		regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32);
746  
747  	regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
748  
749  	if (vco) {
750  		regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
751  				   PLL_VCO_MASK << PLL_VCO_SHIFT,
752  				   vco->val << PLL_VCO_SHIFT);
753  	}
754  
755  	regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
756  			   PLL_ALPHA_EN, PLL_ALPHA_EN);
757  
758  	return clk_alpha_pll_update_latch(pll, is_enabled);
759  }
760  
clk_alpha_pll_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)761  static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
762  				  unsigned long prate)
763  {
764  	return __clk_alpha_pll_set_rate(hw, rate, prate,
765  					clk_alpha_pll_is_enabled);
766  }
767  
clk_alpha_pll_hwfsm_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)768  static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw *hw, unsigned long rate,
769  					unsigned long prate)
770  {
771  	return __clk_alpha_pll_set_rate(hw, rate, prate,
772  					clk_alpha_pll_hwfsm_is_enabled);
773  }
774  
clk_alpha_pll_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)775  static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate,
776  				     unsigned long *prate)
777  {
778  	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
779  	u32 l, alpha_width = pll_alpha_width(pll);
780  	u64 a;
781  	unsigned long min_freq, max_freq;
782  
783  	rate = alpha_pll_round_rate(rate, *prate, &l, &a, alpha_width);
784  	if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
785  		return rate;
786  
787  	min_freq = pll->vco_table[0].min_freq;
788  	max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
789  
790  	return clamp(rate, min_freq, max_freq);
791  }
792  
793  static unsigned long
alpha_huayra_pll_calc_rate(u64 prate,u32 l,u32 a)794  alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a)
795  {
796  	/*
797  	 * a contains 16 bit alpha_val in two’s complement number in the range
798  	 * of [-0.5, 0.5).
799  	 */
800  	if (a >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1))
801  		l -= 1;
802  
803  	return (prate * l) + (prate * a >> PLL_HUAYRA_ALPHA_WIDTH);
804  }
805  
806  static unsigned long
alpha_huayra_pll_round_rate(unsigned long rate,unsigned long prate,u32 * l,u32 * a)807  alpha_huayra_pll_round_rate(unsigned long rate, unsigned long prate,
808  			    u32 *l, u32 *a)
809  {
810  	u64 remainder;
811  	u64 quotient;
812  
813  	quotient = rate;
814  	remainder = do_div(quotient, prate);
815  	*l = quotient;
816  
817  	if (!remainder) {
818  		*a = 0;
819  		return rate;
820  	}
821  
822  	quotient = remainder << PLL_HUAYRA_ALPHA_WIDTH;
823  	remainder = do_div(quotient, prate);
824  
825  	if (remainder)
826  		quotient++;
827  
828  	/*
829  	 * alpha_val should be in two’s complement number in the range
830  	 * of [-0.5, 0.5) so if quotient >= 0.5 then increment the l value
831  	 * since alpha value will be subtracted in this case.
832  	 */
833  	if (quotient >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1))
834  		*l += 1;
835  
836  	*a = quotient;
837  	return alpha_huayra_pll_calc_rate(prate, *l, *a);
838  }
839  
840  static unsigned long
alpha_pll_huayra_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)841  alpha_pll_huayra_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
842  {
843  	u64 rate = parent_rate, tmp;
844  	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
845  	u32 l, alpha = 0, ctl, alpha_m, alpha_n;
846  
847  	regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
848  	regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
849  
850  	if (ctl & PLL_ALPHA_EN) {
851  		regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha);
852  		/*
853  		 * Depending upon alpha_mode, it can be treated as M/N value or
854  		 * as a two’s complement number. When alpha_mode=1,
855  		 * pll_alpha_val<15:8>=M and pll_apla_val<7:0>=N
856  		 *
857  		 *		Fout=FIN*(L+(M/N))
858  		 *
859  		 * M is a signed number (-128 to 127) and N is unsigned
860  		 * (0 to 255). M/N has to be within +/-0.5.
861  		 *
862  		 * When alpha_mode=0, it is a two’s complement number in the
863  		 * range [-0.5, 0.5).
864  		 *
865  		 *		Fout=FIN*(L+(alpha_val)/2^16)
866  		 *
867  		 * where alpha_val is two’s complement number.
868  		 */
869  		if (!(ctl & PLL_ALPHA_MODE))
870  			return alpha_huayra_pll_calc_rate(rate, l, alpha);
871  
872  		alpha_m = alpha >> PLL_HUAYRA_M_SHIFT & PLL_HUAYRA_M_MASK;
873  		alpha_n = alpha >> PLL_HUAYRA_N_SHIFT & PLL_HUAYRA_N_MASK;
874  
875  		rate *= l;
876  		tmp = parent_rate;
877  		if (alpha_m >= BIT(PLL_HUAYRA_M_WIDTH - 1)) {
878  			alpha_m = BIT(PLL_HUAYRA_M_WIDTH) - alpha_m;
879  			tmp *= alpha_m;
880  			do_div(tmp, alpha_n);
881  			rate -= tmp;
882  		} else {
883  			tmp *= alpha_m;
884  			do_div(tmp, alpha_n);
885  			rate += tmp;
886  		}
887  
888  		return rate;
889  	}
890  
891  	return alpha_huayra_pll_calc_rate(rate, l, alpha);
892  }
893  
alpha_pll_huayra_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)894  static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate,
895  				     unsigned long prate)
896  {
897  	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
898  	u32 l, a, ctl, cur_alpha = 0;
899  
900  	rate = alpha_huayra_pll_round_rate(rate, prate, &l, &a);
901  
902  	regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
903  
904  	if (ctl & PLL_ALPHA_EN)
905  		regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha);
906  
907  	/*
908  	 * Huayra PLL supports PLL dynamic programming. User can change L_VAL,
909  	 * without having to go through the power on sequence.
910  	 */
911  	if (clk_alpha_pll_is_enabled(hw)) {
912  		if (cur_alpha != a) {
913  			pr_err("%s: clock needs to be gated\n",
914  			       clk_hw_get_name(hw));
915  			return -EBUSY;
916  		}
917  
918  		regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
919  		/* Ensure that the write above goes to detect L val change. */
920  		mb();
921  		return wait_for_pll_enable_lock(pll);
922  	}
923  
924  	regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
925  	regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
926  
927  	if (a == 0)
928  		regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
929  				   PLL_ALPHA_EN, 0x0);
930  	else
931  		regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
932  				   PLL_ALPHA_EN | PLL_ALPHA_MODE, PLL_ALPHA_EN);
933  
934  	return 0;
935  }
936  
alpha_pll_huayra_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)937  static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,
938  					unsigned long *prate)
939  {
940  	u32 l, a;
941  
942  	return alpha_huayra_pll_round_rate(rate, *prate, &l, &a);
943  }
944  
trion_pll_is_enabled(struct clk_alpha_pll * pll,struct regmap * regmap)945  static int trion_pll_is_enabled(struct clk_alpha_pll *pll,
946  				struct regmap *regmap)
947  {
948  	u32 mode_val, opmode_val;
949  	int ret;
950  
951  	ret = regmap_read(regmap, PLL_MODE(pll), &mode_val);
952  	ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_val);
953  	if (ret)
954  		return 0;
955  
956  	return ((opmode_val & PLL_RUN) && (mode_val & PLL_OUTCTRL));
957  }
958  
clk_trion_pll_is_enabled(struct clk_hw * hw)959  static int clk_trion_pll_is_enabled(struct clk_hw *hw)
960  {
961  	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
962  
963  	return trion_pll_is_enabled(pll, pll->clkr.regmap);
964  }
965  
clk_trion_pll_enable(struct clk_hw * hw)966  static int clk_trion_pll_enable(struct clk_hw *hw)
967  {
968  	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
969  	struct regmap *regmap = pll->clkr.regmap;
970  	u32 val;
971  	int ret;
972  
973  	ret = regmap_read(regmap, PLL_MODE(pll), &val);
974  	if (ret)
975  		return ret;
976  
977  	/* If in FSM mode, just vote for it */
978  	if (val & PLL_VOTE_FSM_ENA) {
979  		ret = clk_enable_regmap(hw);
980  		if (ret)
981  			return ret;
982  		return wait_for_pll_enable_active(pll);
983  	}
984  
985  	/* Set operation mode to RUN */
986  	regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
987  
988  	ret = wait_for_pll_enable_lock(pll);
989  	if (ret)
990  		return ret;
991  
992  	/* Enable the PLL outputs */
993  	ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
994  				 PLL_OUT_MASK, PLL_OUT_MASK);
995  	if (ret)
996  		return ret;
997  
998  	/* Enable the global PLL outputs */
999  	return regmap_update_bits(regmap, PLL_MODE(pll),
1000  				 PLL_OUTCTRL, PLL_OUTCTRL);
1001  }
1002  
clk_trion_pll_disable(struct clk_hw * hw)1003  static void clk_trion_pll_disable(struct clk_hw *hw)
1004  {
1005  	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1006  	struct regmap *regmap = pll->clkr.regmap;
1007  	u32 val;
1008  	int ret;
1009  
1010  	ret = regmap_read(regmap, PLL_MODE(pll), &val);
1011  	if (ret)
1012  		return;
1013  
1014  	/* If in FSM mode, just unvote it */
1015  	if (val & PLL_VOTE_FSM_ENA) {
1016  		clk_disable_regmap(hw);
1017  		return;
1018  	}
1019  
1020  	/* Disable the global PLL output */
1021  	ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1022  	if (ret)
1023  		return;
1024  
1025  	/* Disable the PLL outputs */
1026  	ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
1027  				 PLL_OUT_MASK, 0);
1028  	if (ret)
1029  		return;
1030  
1031  	/* Place the PLL mode in STANDBY */
1032  	regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1033  	regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1034  }
1035  
1036  static unsigned long
clk_trion_pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1037  clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
1038  {
1039  	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1040  	u32 l, frac, alpha_width = pll_alpha_width(pll);
1041  
1042  	regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
1043  	regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac);
1044  
1045  	return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
1046  }
1047  
1048  const struct clk_ops clk_alpha_pll_fixed_ops = {
1049  	.enable = clk_alpha_pll_enable,
1050  	.disable = clk_alpha_pll_disable,
1051  	.is_enabled = clk_alpha_pll_is_enabled,
1052  	.recalc_rate = clk_alpha_pll_recalc_rate,
1053  };
1054  EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_ops);
1055  
1056  const struct clk_ops clk_alpha_pll_ops = {
1057  	.enable = clk_alpha_pll_enable,
1058  	.disable = clk_alpha_pll_disable,
1059  	.is_enabled = clk_alpha_pll_is_enabled,
1060  	.recalc_rate = clk_alpha_pll_recalc_rate,
1061  	.round_rate = clk_alpha_pll_round_rate,
1062  	.set_rate = clk_alpha_pll_set_rate,
1063  };
1064  EXPORT_SYMBOL_GPL(clk_alpha_pll_ops);
1065  
1066  const struct clk_ops clk_alpha_pll_huayra_ops = {
1067  	.enable = clk_alpha_pll_enable,
1068  	.disable = clk_alpha_pll_disable,
1069  	.is_enabled = clk_alpha_pll_is_enabled,
1070  	.recalc_rate = alpha_pll_huayra_recalc_rate,
1071  	.round_rate = alpha_pll_huayra_round_rate,
1072  	.set_rate = alpha_pll_huayra_set_rate,
1073  };
1074  EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops);
1075  
1076  const struct clk_ops clk_alpha_pll_hwfsm_ops = {
1077  	.enable = clk_alpha_pll_hwfsm_enable,
1078  	.disable = clk_alpha_pll_hwfsm_disable,
1079  	.is_enabled = clk_alpha_pll_hwfsm_is_enabled,
1080  	.recalc_rate = clk_alpha_pll_recalc_rate,
1081  	.round_rate = clk_alpha_pll_round_rate,
1082  	.set_rate = clk_alpha_pll_hwfsm_set_rate,
1083  };
1084  EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);
1085  
1086  const struct clk_ops clk_alpha_pll_fixed_trion_ops = {
1087  	.enable = clk_trion_pll_enable,
1088  	.disable = clk_trion_pll_disable,
1089  	.is_enabled = clk_trion_pll_is_enabled,
1090  	.recalc_rate = clk_trion_pll_recalc_rate,
1091  	.round_rate = clk_alpha_pll_round_rate,
1092  };
1093  EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_trion_ops);
1094  
1095  static unsigned long
clk_alpha_pll_postdiv_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1096  clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
1097  {
1098  	struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1099  	u32 ctl;
1100  
1101  	regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
1102  
1103  	ctl >>= PLL_POST_DIV_SHIFT;
1104  	ctl &= PLL_POST_DIV_MASK(pll);
1105  
1106  	return parent_rate >> fls(ctl);
1107  }
1108  
1109  static const struct clk_div_table clk_alpha_div_table[] = {
1110  	{ 0x0, 1 },
1111  	{ 0x1, 2 },
1112  	{ 0x3, 4 },
1113  	{ 0x7, 8 },
1114  	{ 0xf, 16 },
1115  	{ }
1116  };
1117  
1118  static const struct clk_div_table clk_alpha_2bit_div_table[] = {
1119  	{ 0x0, 1 },
1120  	{ 0x1, 2 },
1121  	{ 0x3, 4 },
1122  	{ }
1123  };
1124  
1125  static long
clk_alpha_pll_postdiv_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)1126  clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
1127  				 unsigned long *prate)
1128  {
1129  	struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1130  	const struct clk_div_table *table;
1131  
1132  	if (pll->width == 2)
1133  		table = clk_alpha_2bit_div_table;
1134  	else
1135  		table = clk_alpha_div_table;
1136  
1137  	return divider_round_rate(hw, rate, prate, table,
1138  				  pll->width, CLK_DIVIDER_POWER_OF_TWO);
1139  }
1140  
1141  static long
clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)1142  clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate,
1143  				    unsigned long *prate)
1144  {
1145  	struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1146  	u32 ctl, div;
1147  
1148  	regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
1149  
1150  	ctl >>= PLL_POST_DIV_SHIFT;
1151  	ctl &= BIT(pll->width) - 1;
1152  	div = 1 << fls(ctl);
1153  
1154  	if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)
1155  		*prate = clk_hw_round_rate(clk_hw_get_parent(hw), div * rate);
1156  
1157  	return DIV_ROUND_UP_ULL((u64)*prate, div);
1158  }
1159  
clk_alpha_pll_postdiv_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)1160  static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1161  					  unsigned long parent_rate)
1162  {
1163  	struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1164  	int div;
1165  
1166  	/* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */
1167  	div = DIV_ROUND_UP_ULL(parent_rate, rate) - 1;
1168  
1169  	return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
1170  				  PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
1171  				  div << PLL_POST_DIV_SHIFT);
1172  }
1173  
1174  const struct clk_ops clk_alpha_pll_postdiv_ops = {
1175  	.recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
1176  	.round_rate = clk_alpha_pll_postdiv_round_rate,
1177  	.set_rate = clk_alpha_pll_postdiv_set_rate,
1178  };
1179  EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops);
1180  
1181  const struct clk_ops clk_alpha_pll_postdiv_ro_ops = {
1182  	.round_rate = clk_alpha_pll_postdiv_round_ro_rate,
1183  	.recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
1184  };
1185  EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops);
1186  
clk_fabia_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)1187  void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1188  			     const struct alpha_pll_config *config)
1189  {
1190  	u32 val, mask;
1191  
1192  	clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1193  	clk_alpha_pll_write_config(regmap, PLL_FRAC(pll), config->alpha);
1194  	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
1195  						config->config_ctl_val);
1196  	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
1197  						config->config_ctl_hi_val);
1198  	clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
1199  						config->user_ctl_val);
1200  	clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll),
1201  						config->user_ctl_hi_val);
1202  	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
1203  						config->test_ctl_val);
1204  	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
1205  						config->test_ctl_hi_val);
1206  
1207  	if (config->post_div_mask) {
1208  		mask = config->post_div_mask;
1209  		val = config->post_div_val;
1210  		regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
1211  	}
1212  
1213  	if (pll->flags & SUPPORTS_FSM_LEGACY_MODE)
1214  		regmap_update_bits(regmap, PLL_MODE(pll), PLL_FSM_LEGACY_MODE,
1215  							PLL_FSM_LEGACY_MODE);
1216  
1217  	regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
1218  							PLL_UPDATE_BYPASS);
1219  
1220  	regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1221  }
1222  EXPORT_SYMBOL_GPL(clk_fabia_pll_configure);
1223  
alpha_pll_fabia_enable(struct clk_hw * hw)1224  static int alpha_pll_fabia_enable(struct clk_hw *hw)
1225  {
1226  	int ret;
1227  	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1228  	u32 val, opmode_val;
1229  	struct regmap *regmap = pll->clkr.regmap;
1230  
1231  	ret = regmap_read(regmap, PLL_MODE(pll), &val);
1232  	if (ret)
1233  		return ret;
1234  
1235  	/* If in FSM mode, just vote for it */
1236  	if (val & PLL_VOTE_FSM_ENA) {
1237  		ret = clk_enable_regmap(hw);
1238  		if (ret)
1239  			return ret;
1240  		return wait_for_pll_enable_active(pll);
1241  	}
1242  
1243  	ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val);
1244  	if (ret)
1245  		return ret;
1246  
1247  	/* Skip If PLL is already running */
1248  	if ((opmode_val & PLL_RUN) && (val & PLL_OUTCTRL))
1249  		return 0;
1250  
1251  	ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1252  	if (ret)
1253  		return ret;
1254  
1255  	ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1256  	if (ret)
1257  		return ret;
1258  
1259  	ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N,
1260  				 PLL_RESET_N);
1261  	if (ret)
1262  		return ret;
1263  
1264  	ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
1265  	if (ret)
1266  		return ret;
1267  
1268  	ret = wait_for_pll_enable_lock(pll);
1269  	if (ret)
1270  		return ret;
1271  
1272  	ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
1273  				 PLL_OUT_MASK, PLL_OUT_MASK);
1274  	if (ret)
1275  		return ret;
1276  
1277  	return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL,
1278  				 PLL_OUTCTRL);
1279  }
1280  
alpha_pll_fabia_disable(struct clk_hw * hw)1281  static void alpha_pll_fabia_disable(struct clk_hw *hw)
1282  {
1283  	int ret;
1284  	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1285  	u32 val;
1286  	struct regmap *regmap = pll->clkr.regmap;
1287  
1288  	ret = regmap_read(regmap, PLL_MODE(pll), &val);
1289  	if (ret)
1290  		return;
1291  
1292  	/* If in FSM mode, just unvote it */
1293  	if (val & PLL_FSM_ENA) {
1294  		clk_disable_regmap(hw);
1295  		return;
1296  	}
1297  
1298  	ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1299  	if (ret)
1300  		return;
1301  
1302  	/* Disable main outputs */
1303  	ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
1304  	if (ret)
1305  		return;
1306  
1307  	/* Place the PLL in STANDBY */
1308  	regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1309  }
1310  
alpha_pll_fabia_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1311  static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw,
1312  						unsigned long parent_rate)
1313  {
1314  	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1315  	u32 l, frac, alpha_width = pll_alpha_width(pll);
1316  
1317  	regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
1318  	regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac);
1319  
1320  	return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
1321  }
1322  
1323  /*
1324   * Due to limited number of bits for fractional rate programming, the
1325   * rounded up rate could be marginally higher than the requested rate.
1326   */
alpha_pll_check_rate_margin(struct clk_hw * hw,unsigned long rrate,unsigned long rate)1327  static int alpha_pll_check_rate_margin(struct clk_hw *hw,
1328  			unsigned long rrate, unsigned long rate)
1329  {
1330  	unsigned long rate_margin = rate + PLL_RATE_MARGIN;
1331  
1332  	if (rrate > rate_margin || rrate < rate) {
1333  		pr_err("%s: Rounded rate %lu not within range [%lu, %lu)\n",
1334  		       clk_hw_get_name(hw), rrate, rate, rate_margin);
1335  		return -EINVAL;
1336  	}
1337  
1338  	return 0;
1339  }
1340  
alpha_pll_fabia_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)1341  static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate,
1342  						unsigned long prate)
1343  {
1344  	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1345  	u32 l, alpha_width = pll_alpha_width(pll);
1346  	unsigned long rrate;
1347  	int ret;
1348  	u64 a;
1349  
1350  	rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
1351  
1352  	ret = alpha_pll_check_rate_margin(hw, rrate, rate);
1353  	if (ret < 0)
1354  		return ret;
1355  
1356  	regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
1357  	regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a);
1358  
1359  	return __clk_alpha_pll_update_latch(pll);
1360  }
1361  
alpha_pll_fabia_prepare(struct clk_hw * hw)1362  static int alpha_pll_fabia_prepare(struct clk_hw *hw)
1363  {
1364  	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1365  	const struct pll_vco *vco;
1366  	struct clk_hw *parent_hw;
1367  	unsigned long cal_freq, rrate;
1368  	u32 cal_l, val, alpha_width = pll_alpha_width(pll);
1369  	const char *name = clk_hw_get_name(hw);
1370  	u64 a;
1371  	int ret;
1372  
1373  	/* Check if calibration needs to be done i.e. PLL is in reset */
1374  	ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1375  	if (ret)
1376  		return ret;
1377  
1378  	/* Return early if calibration is not needed. */
1379  	if (val & PLL_RESET_N)
1380  		return 0;
1381  
1382  	vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw));
1383  	if (!vco) {
1384  		pr_err("%s: alpha pll not in a valid vco range\n", name);
1385  		return -EINVAL;
1386  	}
1387  
1388  	cal_freq = DIV_ROUND_CLOSEST((pll->vco_table[0].min_freq +
1389  				pll->vco_table[0].max_freq) * 54, 100);
1390  
1391  	parent_hw = clk_hw_get_parent(hw);
1392  	if (!parent_hw)
1393  		return -EINVAL;
1394  
1395  	rrate = alpha_pll_round_rate(cal_freq, clk_hw_get_rate(parent_hw),
1396  					&cal_l, &a, alpha_width);
1397  
1398  	ret = alpha_pll_check_rate_margin(hw, rrate, cal_freq);
1399  	if (ret < 0)
1400  		return ret;
1401  
1402  	/* Setup PLL for calibration frequency */
1403  	regmap_write(pll->clkr.regmap, PLL_CAL_L_VAL(pll), cal_l);
1404  
1405  	/* Bringup the PLL at calibration frequency */
1406  	ret = clk_alpha_pll_enable(hw);
1407  	if (ret) {
1408  		pr_err("%s: alpha pll calibration failed\n", name);
1409  		return ret;
1410  	}
1411  
1412  	clk_alpha_pll_disable(hw);
1413  
1414  	return 0;
1415  }
1416  
1417  const struct clk_ops clk_alpha_pll_fabia_ops = {
1418  	.prepare = alpha_pll_fabia_prepare,
1419  	.enable = alpha_pll_fabia_enable,
1420  	.disable = alpha_pll_fabia_disable,
1421  	.is_enabled = clk_alpha_pll_is_enabled,
1422  	.set_rate = alpha_pll_fabia_set_rate,
1423  	.recalc_rate = alpha_pll_fabia_recalc_rate,
1424  	.round_rate = clk_alpha_pll_round_rate,
1425  };
1426  EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops);
1427  
1428  const struct clk_ops clk_alpha_pll_fixed_fabia_ops = {
1429  	.enable = alpha_pll_fabia_enable,
1430  	.disable = alpha_pll_fabia_disable,
1431  	.is_enabled = clk_alpha_pll_is_enabled,
1432  	.recalc_rate = alpha_pll_fabia_recalc_rate,
1433  	.round_rate = clk_alpha_pll_round_rate,
1434  };
1435  EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops);
1436  
clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1437  static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw,
1438  					unsigned long parent_rate)
1439  {
1440  	struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1441  	u32 i, div = 1, val;
1442  	int ret;
1443  
1444  	ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
1445  	if (ret)
1446  		return ret;
1447  
1448  	val >>= pll->post_div_shift;
1449  	val &= BIT(pll->width) - 1;
1450  
1451  	for (i = 0; i < pll->num_post_div; i++) {
1452  		if (pll->post_div_table[i].val == val) {
1453  			div = pll->post_div_table[i].div;
1454  			break;
1455  		}
1456  	}
1457  
1458  	return (parent_rate / div);
1459  }
1460  
1461  static unsigned long
clk_trion_pll_postdiv_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1462  clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
1463  {
1464  	struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1465  	struct regmap *regmap = pll->clkr.regmap;
1466  	u32 i, div = 1, val;
1467  
1468  	regmap_read(regmap, PLL_USER_CTL(pll), &val);
1469  
1470  	val >>= pll->post_div_shift;
1471  	val &= PLL_POST_DIV_MASK(pll);
1472  
1473  	for (i = 0; i < pll->num_post_div; i++) {
1474  		if (pll->post_div_table[i].val == val) {
1475  			div = pll->post_div_table[i].div;
1476  			break;
1477  		}
1478  	}
1479  
1480  	return (parent_rate / div);
1481  }
1482  
1483  static long
clk_trion_pll_postdiv_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)1484  clk_trion_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
1485  				 unsigned long *prate)
1486  {
1487  	struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1488  
1489  	return divider_round_rate(hw, rate, prate, pll->post_div_table,
1490  				  pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1491  };
1492  
1493  static int
clk_trion_pll_postdiv_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)1494  clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1495  			       unsigned long parent_rate)
1496  {
1497  	struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1498  	struct regmap *regmap = pll->clkr.regmap;
1499  	int i, val = 0, div;
1500  
1501  	div = DIV_ROUND_UP_ULL(parent_rate, rate);
1502  	for (i = 0; i < pll->num_post_div; i++) {
1503  		if (pll->post_div_table[i].div == div) {
1504  			val = pll->post_div_table[i].val;
1505  			break;
1506  		}
1507  	}
1508  
1509  	return regmap_update_bits(regmap, PLL_USER_CTL(pll),
1510  				  PLL_POST_DIV_MASK(pll) << pll->post_div_shift,
1511  				  val << pll->post_div_shift);
1512  }
1513  
1514  const struct clk_ops clk_alpha_pll_postdiv_trion_ops = {
1515  	.recalc_rate = clk_trion_pll_postdiv_recalc_rate,
1516  	.round_rate = clk_trion_pll_postdiv_round_rate,
1517  	.set_rate = clk_trion_pll_postdiv_set_rate,
1518  };
1519  EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_trion_ops);
1520  
clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)1521  static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw,
1522  				unsigned long rate, unsigned long *prate)
1523  {
1524  	struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1525  
1526  	return divider_round_rate(hw, rate, prate, pll->post_div_table,
1527  				pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1528  }
1529  
clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)1530  static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw,
1531  				unsigned long rate, unsigned long parent_rate)
1532  {
1533  	struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1534  	int i, val = 0, div, ret;
1535  
1536  	/*
1537  	 * If the PLL is in FSM mode, then treat set_rate callback as a
1538  	 * no-operation.
1539  	 */
1540  	ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1541  	if (ret)
1542  		return ret;
1543  
1544  	if (val & PLL_VOTE_FSM_ENA)
1545  		return 0;
1546  
1547  	div = DIV_ROUND_UP_ULL(parent_rate, rate);
1548  	for (i = 0; i < pll->num_post_div; i++) {
1549  		if (pll->post_div_table[i].div == div) {
1550  			val = pll->post_div_table[i].val;
1551  			break;
1552  		}
1553  	}
1554  
1555  	return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
1556  				(BIT(pll->width) - 1) << pll->post_div_shift,
1557  				val << pll->post_div_shift);
1558  }
1559  
1560  const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = {
1561  	.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
1562  	.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
1563  	.set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
1564  };
1565  EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops);
1566  
1567  /**
1568   * clk_trion_pll_configure - configure the trion pll
1569   *
1570   * @pll: clk alpha pll
1571   * @regmap: register map
1572   * @config: configuration to apply for pll
1573   */
clk_trion_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)1574  void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1575  			     const struct alpha_pll_config *config)
1576  {
1577  	/*
1578  	 * If the bootloader left the PLL enabled it's likely that there are
1579  	 * RCGs that will lock up if we disable the PLL below.
1580  	 */
1581  	if (trion_pll_is_enabled(pll, regmap)) {
1582  		pr_debug("Trion PLL is already enabled, skipping configuration\n");
1583  		return;
1584  	}
1585  
1586  	clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1587  	regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL);
1588  	clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
1589  	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
1590  				     config->config_ctl_val);
1591  	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
1592  				     config->config_ctl_hi_val);
1593  	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll),
1594  				     config->config_ctl_hi1_val);
1595  	clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
1596  					config->user_ctl_val);
1597  	clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll),
1598  					config->user_ctl_hi_val);
1599  	clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll),
1600  					config->user_ctl_hi1_val);
1601  	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
1602  					config->test_ctl_val);
1603  	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
1604  					config->test_ctl_hi_val);
1605  	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll),
1606  					config->test_ctl_hi1_val);
1607  
1608  	regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
1609  			   PLL_UPDATE_BYPASS);
1610  
1611  	/* Disable PLL output */
1612  	regmap_update_bits(regmap, PLL_MODE(pll),  PLL_OUTCTRL, 0);
1613  
1614  	/* Set operation mode to OFF */
1615  	regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1616  
1617  	/* Place the PLL in STANDBY mode */
1618  	regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1619  }
1620  EXPORT_SYMBOL_GPL(clk_trion_pll_configure);
1621  
1622  /*
1623   * The TRION PLL requires a power-on self-calibration which happens when the
1624   * PLL comes out of reset. Calibrate in case it is not completed.
1625   */
__alpha_pll_trion_prepare(struct clk_hw * hw,u32 pcal_done)1626  static int __alpha_pll_trion_prepare(struct clk_hw *hw, u32 pcal_done)
1627  {
1628  	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1629  	u32 val;
1630  	int ret;
1631  
1632  	/* Return early if calibration is not needed. */
1633  	regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &val);
1634  	if (val & pcal_done)
1635  		return 0;
1636  
1637  	/* On/off to calibrate */
1638  	ret = clk_trion_pll_enable(hw);
1639  	if (!ret)
1640  		clk_trion_pll_disable(hw);
1641  
1642  	return ret;
1643  }
1644  
alpha_pll_trion_prepare(struct clk_hw * hw)1645  static int alpha_pll_trion_prepare(struct clk_hw *hw)
1646  {
1647  	return __alpha_pll_trion_prepare(hw, TRION_PCAL_DONE);
1648  }
1649  
alpha_pll_lucid_prepare(struct clk_hw * hw)1650  static int alpha_pll_lucid_prepare(struct clk_hw *hw)
1651  {
1652  	return __alpha_pll_trion_prepare(hw, LUCID_PCAL_DONE);
1653  }
1654  
__alpha_pll_trion_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate,u32 latch_bit,u32 latch_ack)1655  static int __alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,
1656  				      unsigned long prate, u32 latch_bit, u32 latch_ack)
1657  {
1658  	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1659  	unsigned long rrate;
1660  	u32 val, l, alpha_width = pll_alpha_width(pll);
1661  	u64 a;
1662  	int ret;
1663  
1664  	rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
1665  
1666  	ret = alpha_pll_check_rate_margin(hw, rrate, rate);
1667  	if (ret < 0)
1668  		return ret;
1669  
1670  	regmap_update_bits(pll->clkr.regmap, PLL_L_VAL(pll), LUCID_EVO_PLL_L_VAL_MASK,  l);
1671  	regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
1672  
1673  	/* Latch the PLL input */
1674  	ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, latch_bit);
1675  	if (ret)
1676  		return ret;
1677  
1678  	/* Wait for 2 reference cycles before checking the ACK bit. */
1679  	udelay(1);
1680  	regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1681  	if (!(val & latch_ack)) {
1682  		pr_err("Lucid PLL latch failed. Output may be unstable!\n");
1683  		return -EINVAL;
1684  	}
1685  
1686  	/* Return the latch input to 0 */
1687  	ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, 0);
1688  	if (ret)
1689  		return ret;
1690  
1691  	if (clk_hw_is_enabled(hw)) {
1692  		ret = wait_for_pll_enable_lock(pll);
1693  		if (ret)
1694  			return ret;
1695  	}
1696  
1697  	/* Wait for PLL output to stabilize */
1698  	udelay(100);
1699  	return 0;
1700  }
1701  
alpha_pll_trion_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)1702  static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,
1703  				    unsigned long prate)
1704  {
1705  	return __alpha_pll_trion_set_rate(hw, rate, prate, PLL_UPDATE, ALPHA_PLL_ACK_LATCH);
1706  }
1707  
1708  const struct clk_ops clk_alpha_pll_trion_ops = {
1709  	.prepare = alpha_pll_trion_prepare,
1710  	.enable = clk_trion_pll_enable,
1711  	.disable = clk_trion_pll_disable,
1712  	.is_enabled = clk_trion_pll_is_enabled,
1713  	.recalc_rate = clk_trion_pll_recalc_rate,
1714  	.round_rate = clk_alpha_pll_round_rate,
1715  	.set_rate = alpha_pll_trion_set_rate,
1716  };
1717  EXPORT_SYMBOL_GPL(clk_alpha_pll_trion_ops);
1718  
1719  const struct clk_ops clk_alpha_pll_lucid_ops = {
1720  	.prepare = alpha_pll_lucid_prepare,
1721  	.enable = clk_trion_pll_enable,
1722  	.disable = clk_trion_pll_disable,
1723  	.is_enabled = clk_trion_pll_is_enabled,
1724  	.recalc_rate = clk_trion_pll_recalc_rate,
1725  	.round_rate = clk_alpha_pll_round_rate,
1726  	.set_rate = alpha_pll_trion_set_rate,
1727  };
1728  EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops);
1729  
1730  const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = {
1731  	.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
1732  	.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
1733  	.set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
1734  };
1735  EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops);
1736  
clk_agera_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)1737  void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1738  			const struct alpha_pll_config *config)
1739  {
1740  	clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1741  	clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
1742  	clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
1743  							config->user_ctl_val);
1744  	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
1745  						config->config_ctl_val);
1746  	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
1747  						config->config_ctl_hi_val);
1748  	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
1749  						config->test_ctl_val);
1750  	clk_alpha_pll_write_config(regmap,  PLL_TEST_CTL_U(pll),
1751  						config->test_ctl_hi_val);
1752  }
1753  EXPORT_SYMBOL_GPL(clk_agera_pll_configure);
1754  
clk_alpha_pll_agera_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)1755  static int clk_alpha_pll_agera_set_rate(struct clk_hw *hw, unsigned long rate,
1756  							unsigned long prate)
1757  {
1758  	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1759  	u32 l, alpha_width = pll_alpha_width(pll);
1760  	int ret;
1761  	unsigned long rrate;
1762  	u64 a;
1763  
1764  	rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
1765  	ret = alpha_pll_check_rate_margin(hw, rrate, rate);
1766  	if (ret < 0)
1767  		return ret;
1768  
1769  	/* change L_VAL without having to go through the power on sequence */
1770  	regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
1771  	regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
1772  
1773  	if (clk_hw_is_enabled(hw))
1774  		return wait_for_pll_enable_lock(pll);
1775  
1776  	return 0;
1777  }
1778  
1779  const struct clk_ops clk_alpha_pll_agera_ops = {
1780  	.enable = clk_alpha_pll_enable,
1781  	.disable = clk_alpha_pll_disable,
1782  	.is_enabled = clk_alpha_pll_is_enabled,
1783  	.recalc_rate = alpha_pll_fabia_recalc_rate,
1784  	.round_rate = clk_alpha_pll_round_rate,
1785  	.set_rate = clk_alpha_pll_agera_set_rate,
1786  };
1787  EXPORT_SYMBOL_GPL(clk_alpha_pll_agera_ops);
1788  
1789  /**
1790   * clk_lucid_5lpe_pll_configure - configure the lucid 5lpe pll
1791   *
1792   * @pll: clk alpha pll
1793   * @regmap: register map
1794   * @config: configuration to apply for pll
1795   */
clk_lucid_5lpe_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)1796  void clk_lucid_5lpe_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1797  				  const struct alpha_pll_config *config)
1798  {
1799  	/*
1800  	 * If the bootloader left the PLL enabled it's likely that there are
1801  	 * RCGs that will lock up if we disable the PLL below.
1802  	 */
1803  	if (trion_pll_is_enabled(pll, regmap)) {
1804  		pr_debug("Lucid 5LPE PLL is already enabled, skipping configuration\n");
1805  		return;
1806  	}
1807  
1808  	clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1809  	regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL);
1810  	clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
1811  	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
1812  				     config->config_ctl_val);
1813  	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
1814  				     config->config_ctl_hi_val);
1815  	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll),
1816  				     config->config_ctl_hi1_val);
1817  	clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
1818  					config->user_ctl_val);
1819  	clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll),
1820  					config->user_ctl_hi_val);
1821  	clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll),
1822  					config->user_ctl_hi1_val);
1823  	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
1824  					config->test_ctl_val);
1825  	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
1826  					config->test_ctl_hi_val);
1827  	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll),
1828  					config->test_ctl_hi1_val);
1829  
1830  	/* Disable PLL output */
1831  	regmap_update_bits(regmap, PLL_MODE(pll),  PLL_OUTCTRL, 0);
1832  
1833  	/* Set operation mode to OFF */
1834  	regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1835  
1836  	/* Place the PLL in STANDBY mode */
1837  	regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1838  }
1839  EXPORT_SYMBOL_GPL(clk_lucid_5lpe_pll_configure);
1840  
alpha_pll_lucid_5lpe_enable(struct clk_hw * hw)1841  static int alpha_pll_lucid_5lpe_enable(struct clk_hw *hw)
1842  {
1843  	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1844  	u32 val;
1845  	int ret;
1846  
1847  	ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
1848  	if (ret)
1849  		return ret;
1850  
1851  	/* If in FSM mode, just vote for it */
1852  	if (val & LUCID_5LPE_ENABLE_VOTE_RUN) {
1853  		ret = clk_enable_regmap(hw);
1854  		if (ret)
1855  			return ret;
1856  		return wait_for_pll_enable_lock(pll);
1857  	}
1858  
1859  	/* Check if PLL is already enabled, return if enabled */
1860  	ret = trion_pll_is_enabled(pll, pll->clkr.regmap);
1861  	if (ret < 0)
1862  		return ret;
1863  
1864  	ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1865  	if (ret)
1866  		return ret;
1867  
1868  	regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN);
1869  
1870  	ret = wait_for_pll_enable_lock(pll);
1871  	if (ret)
1872  		return ret;
1873  
1874  	/* Enable the PLL outputs */
1875  	ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK);
1876  	if (ret)
1877  		return ret;
1878  
1879  	/* Enable the global PLL outputs */
1880  	return regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
1881  }
1882  
alpha_pll_lucid_5lpe_disable(struct clk_hw * hw)1883  static void alpha_pll_lucid_5lpe_disable(struct clk_hw *hw)
1884  {
1885  	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1886  	u32 val;
1887  	int ret;
1888  
1889  	ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
1890  	if (ret)
1891  		return;
1892  
1893  	/* If in FSM mode, just unvote it */
1894  	if (val & LUCID_5LPE_ENABLE_VOTE_RUN) {
1895  		clk_disable_regmap(hw);
1896  		return;
1897  	}
1898  
1899  	/* Disable the global PLL output */
1900  	ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1901  	if (ret)
1902  		return;
1903  
1904  	/* Disable the PLL outputs */
1905  	ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
1906  	if (ret)
1907  		return;
1908  
1909  	/* Place the PLL mode in STANDBY */
1910  	regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY);
1911  }
1912  
1913  /*
1914   * The Lucid 5LPE PLL requires a power-on self-calibration which happens
1915   * when the PLL comes out of reset. Calibrate in case it is not completed.
1916   */
alpha_pll_lucid_5lpe_prepare(struct clk_hw * hw)1917  static int alpha_pll_lucid_5lpe_prepare(struct clk_hw *hw)
1918  {
1919  	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1920  	struct clk_hw *p;
1921  	u32 val = 0;
1922  	int ret;
1923  
1924  	/* Return early if calibration is not needed. */
1925  	regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1926  	if (val & LUCID_5LPE_PCAL_DONE)
1927  		return 0;
1928  
1929  	p = clk_hw_get_parent(hw);
1930  	if (!p)
1931  		return -EINVAL;
1932  
1933  	ret = alpha_pll_lucid_5lpe_enable(hw);
1934  	if (ret)
1935  		return ret;
1936  
1937  	alpha_pll_lucid_5lpe_disable(hw);
1938  
1939  	return 0;
1940  }
1941  
alpha_pll_lucid_5lpe_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)1942  static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate,
1943  					 unsigned long prate)
1944  {
1945  	return __alpha_pll_trion_set_rate(hw, rate, prate,
1946  					  LUCID_5LPE_PLL_LATCH_INPUT,
1947  					  LUCID_5LPE_ALPHA_PLL_ACK_LATCH);
1948  }
1949  
__clk_lucid_pll_postdiv_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate,unsigned long enable_vote_run)1950  static int __clk_lucid_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1951  					    unsigned long parent_rate,
1952  					    unsigned long enable_vote_run)
1953  {
1954  	struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1955  	struct regmap *regmap = pll->clkr.regmap;
1956  	int i, val, div, ret;
1957  	u32 mask;
1958  
1959  	/*
1960  	 * If the PLL is in FSM mode, then treat set_rate callback as a
1961  	 * no-operation.
1962  	 */
1963  	ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
1964  	if (ret)
1965  		return ret;
1966  
1967  	if (val & enable_vote_run)
1968  		return 0;
1969  
1970  	if (!pll->post_div_table) {
1971  		pr_err("Missing the post_div_table for the %s PLL\n",
1972  		       clk_hw_get_name(&pll->clkr.hw));
1973  		return -EINVAL;
1974  	}
1975  
1976  	div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
1977  	for (i = 0; i < pll->num_post_div; i++) {
1978  		if (pll->post_div_table[i].div == div) {
1979  			val = pll->post_div_table[i].val;
1980  			break;
1981  		}
1982  	}
1983  
1984  	mask = GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift);
1985  	return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
1986  				  mask, val << pll->post_div_shift);
1987  }
1988  
clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)1989  static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1990  					       unsigned long parent_rate)
1991  {
1992  	return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_5LPE_ENABLE_VOTE_RUN);
1993  }
1994  
1995  const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = {
1996  	.prepare = alpha_pll_lucid_5lpe_prepare,
1997  	.enable = alpha_pll_lucid_5lpe_enable,
1998  	.disable = alpha_pll_lucid_5lpe_disable,
1999  	.is_enabled = clk_trion_pll_is_enabled,
2000  	.recalc_rate = clk_trion_pll_recalc_rate,
2001  	.round_rate = clk_alpha_pll_round_rate,
2002  	.set_rate = alpha_pll_lucid_5lpe_set_rate,
2003  };
2004  EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_5lpe_ops);
2005  
2006  const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = {
2007  	.enable = alpha_pll_lucid_5lpe_enable,
2008  	.disable = alpha_pll_lucid_5lpe_disable,
2009  	.is_enabled = clk_trion_pll_is_enabled,
2010  	.recalc_rate = clk_trion_pll_recalc_rate,
2011  	.round_rate = clk_alpha_pll_round_rate,
2012  };
2013  EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_5lpe_ops);
2014  
2015  const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = {
2016  	.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
2017  	.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
2018  	.set_rate = clk_lucid_5lpe_pll_postdiv_set_rate,
2019  };
2020  EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_5lpe_ops);
2021  
clk_zonda_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)2022  void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2023  			     const struct alpha_pll_config *config)
2024  {
2025  	clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
2026  	clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
2027  	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2028  	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
2029  	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
2030  	clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
2031  	clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
2032  	clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val);
2033  	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2034  	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2035  	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
2036  
2037  	regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, 0);
2038  
2039  	/* Disable PLL output */
2040  	regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2041  
2042  	/* Set operation mode to OFF */
2043  	regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2044  
2045  	/* Place the PLL in STANDBY mode */
2046  	regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2047  }
2048  EXPORT_SYMBOL_GPL(clk_zonda_pll_configure);
2049  
clk_zonda_pll_enable(struct clk_hw * hw)2050  static int clk_zonda_pll_enable(struct clk_hw *hw)
2051  {
2052  	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2053  	struct regmap *regmap = pll->clkr.regmap;
2054  	u32 val;
2055  	int ret;
2056  
2057  	regmap_read(regmap, PLL_MODE(pll), &val);
2058  
2059  	/* If in FSM mode, just vote for it */
2060  	if (val & PLL_VOTE_FSM_ENA) {
2061  		ret = clk_enable_regmap(hw);
2062  		if (ret)
2063  			return ret;
2064  		return wait_for_pll_enable_active(pll);
2065  	}
2066  
2067  	/* Get the PLL out of bypass mode */
2068  	regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL);
2069  
2070  	/*
2071  	 * H/W requires a 1us delay between disabling the bypass and
2072  	 * de-asserting the reset.
2073  	 */
2074  	udelay(1);
2075  
2076  	regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2077  
2078  	/* Set operation mode to RUN */
2079  	regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
2080  
2081  	regmap_read(regmap, PLL_TEST_CTL(pll), &val);
2082  
2083  	/* If cfa mode then poll for freq lock */
2084  	if (val & ZONDA_STAY_IN_CFA)
2085  		ret = wait_for_zonda_pll_freq_lock(pll);
2086  	else
2087  		ret = wait_for_pll_enable_lock(pll);
2088  	if (ret)
2089  		return ret;
2090  
2091  	/* Enable the PLL outputs */
2092  	regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK);
2093  
2094  	/* Enable the global PLL outputs */
2095  	regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
2096  
2097  	return 0;
2098  }
2099  
clk_zonda_pll_disable(struct clk_hw * hw)2100  static void clk_zonda_pll_disable(struct clk_hw *hw)
2101  {
2102  	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2103  	struct regmap *regmap = pll->clkr.regmap;
2104  	u32 val;
2105  
2106  	regmap_read(regmap, PLL_MODE(pll), &val);
2107  
2108  	/* If in FSM mode, just unvote it */
2109  	if (val & PLL_VOTE_FSM_ENA) {
2110  		clk_disable_regmap(hw);
2111  		return;
2112  	}
2113  
2114  	/* Disable the global PLL output */
2115  	regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2116  
2117  	/* Disable the PLL outputs */
2118  	regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, 0);
2119  
2120  	/* Put the PLL in bypass and reset */
2121  	regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, 0);
2122  
2123  	/* Place the PLL mode in OFF state */
2124  	regmap_write(regmap, PLL_OPMODE(pll), 0x0);
2125  }
2126  
clk_zonda_pll_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)2127  static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate,
2128  				  unsigned long prate)
2129  {
2130  	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2131  	unsigned long rrate;
2132  	u32 test_ctl_val;
2133  	u32 l, alpha_width = pll_alpha_width(pll);
2134  	u64 a;
2135  	int ret;
2136  
2137  	rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
2138  
2139  	ret = alpha_pll_check_rate_margin(hw, rrate, rate);
2140  	if (ret < 0)
2141  		return ret;
2142  
2143  	regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
2144  	regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
2145  
2146  	/* Wait before polling for the frequency latch */
2147  	udelay(5);
2148  
2149  	/* Read stay in cfa mode */
2150  	regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val);
2151  
2152  	/* If cfa mode then poll for freq lock */
2153  	if (test_ctl_val & ZONDA_STAY_IN_CFA)
2154  		ret = wait_for_zonda_pll_freq_lock(pll);
2155  	else
2156  		ret = wait_for_pll_enable_lock(pll);
2157  	if (ret)
2158  		return ret;
2159  
2160  	/* Wait for PLL output to stabilize */
2161  	udelay(100);
2162  	return 0;
2163  }
2164  
2165  const struct clk_ops clk_alpha_pll_zonda_ops = {
2166  	.enable = clk_zonda_pll_enable,
2167  	.disable = clk_zonda_pll_disable,
2168  	.is_enabled = clk_trion_pll_is_enabled,
2169  	.recalc_rate = clk_trion_pll_recalc_rate,
2170  	.round_rate = clk_alpha_pll_round_rate,
2171  	.set_rate = clk_zonda_pll_set_rate,
2172  };
2173  EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops);
2174  
clk_lucid_evo_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)2175  void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2176  				 const struct alpha_pll_config *config)
2177  {
2178  	u32 lval = config->l;
2179  
2180  	lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT;
2181  	clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval);
2182  	clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
2183  	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2184  	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
2185  	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
2186  	clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
2187  	clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
2188  	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2189  	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2190  	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
2191  	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val);
2192  
2193  	/* Disable PLL output */
2194  	regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2195  
2196  	/* Set operation mode to STANDBY and de-assert the reset */
2197  	regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2198  	regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2199  }
2200  EXPORT_SYMBOL_GPL(clk_lucid_evo_pll_configure);
2201  
alpha_pll_lucid_evo_enable(struct clk_hw * hw)2202  static int alpha_pll_lucid_evo_enable(struct clk_hw *hw)
2203  {
2204  	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2205  	struct regmap *regmap = pll->clkr.regmap;
2206  	u32 val;
2207  	int ret;
2208  
2209  	ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
2210  	if (ret)
2211  		return ret;
2212  
2213  	/* If in FSM mode, just vote for it */
2214  	if (val & LUCID_EVO_ENABLE_VOTE_RUN) {
2215  		ret = clk_enable_regmap(hw);
2216  		if (ret)
2217  			return ret;
2218  		return wait_for_pll_enable_lock(pll);
2219  	}
2220  
2221  	/* Check if PLL is already enabled */
2222  	ret = trion_pll_is_enabled(pll, regmap);
2223  	if (ret < 0) {
2224  		return ret;
2225  	} else if (ret) {
2226  		pr_warn("%s PLL is already enabled\n", clk_hw_get_name(&pll->clkr.hw));
2227  		return 0;
2228  	}
2229  
2230  	ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2231  	if (ret)
2232  		return ret;
2233  
2234  	/* Set operation mode to RUN */
2235  	regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
2236  
2237  	ret = wait_for_pll_enable_lock(pll);
2238  	if (ret)
2239  		return ret;
2240  
2241  	/* Enable the PLL outputs */
2242  	ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK);
2243  	if (ret)
2244  		return ret;
2245  
2246  	/* Enable the global PLL outputs */
2247  	ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
2248  	if (ret)
2249  		return ret;
2250  
2251  	/* Ensure that the write above goes through before returning. */
2252  	mb();
2253  	return ret;
2254  }
2255  
_alpha_pll_lucid_evo_disable(struct clk_hw * hw,bool reset)2256  static void _alpha_pll_lucid_evo_disable(struct clk_hw *hw, bool reset)
2257  {
2258  	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2259  	struct regmap *regmap = pll->clkr.regmap;
2260  	u32 val;
2261  	int ret;
2262  
2263  	ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
2264  	if (ret)
2265  		return;
2266  
2267  	/* If in FSM mode, just unvote it */
2268  	if (val & LUCID_EVO_ENABLE_VOTE_RUN) {
2269  		clk_disable_regmap(hw);
2270  		return;
2271  	}
2272  
2273  	/* Disable the global PLL output */
2274  	ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2275  	if (ret)
2276  		return;
2277  
2278  	/* Disable the PLL outputs */
2279  	ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
2280  	if (ret)
2281  		return;
2282  
2283  	/* Place the PLL mode in STANDBY */
2284  	regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2285  
2286  	if (reset)
2287  		regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 0);
2288  }
2289  
_alpha_pll_lucid_evo_prepare(struct clk_hw * hw,bool reset)2290  static int _alpha_pll_lucid_evo_prepare(struct clk_hw *hw, bool reset)
2291  {
2292  	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2293  	struct clk_hw *p;
2294  	u32 val = 0;
2295  	int ret;
2296  
2297  	/* Return early if calibration is not needed. */
2298  	regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
2299  	if (!(val & LUCID_EVO_PCAL_NOT_DONE))
2300  		return 0;
2301  
2302  	p = clk_hw_get_parent(hw);
2303  	if (!p)
2304  		return -EINVAL;
2305  
2306  	ret = alpha_pll_lucid_evo_enable(hw);
2307  	if (ret)
2308  		return ret;
2309  
2310  	_alpha_pll_lucid_evo_disable(hw, reset);
2311  
2312  	return 0;
2313  }
2314  
alpha_pll_lucid_evo_disable(struct clk_hw * hw)2315  static void alpha_pll_lucid_evo_disable(struct clk_hw *hw)
2316  {
2317  	_alpha_pll_lucid_evo_disable(hw, false);
2318  }
2319  
alpha_pll_lucid_evo_prepare(struct clk_hw * hw)2320  static int alpha_pll_lucid_evo_prepare(struct clk_hw *hw)
2321  {
2322  	return _alpha_pll_lucid_evo_prepare(hw, false);
2323  }
2324  
alpha_pll_reset_lucid_evo_disable(struct clk_hw * hw)2325  static void alpha_pll_reset_lucid_evo_disable(struct clk_hw *hw)
2326  {
2327  	_alpha_pll_lucid_evo_disable(hw, true);
2328  }
2329  
alpha_pll_reset_lucid_evo_prepare(struct clk_hw * hw)2330  static int alpha_pll_reset_lucid_evo_prepare(struct clk_hw *hw)
2331  {
2332  	return _alpha_pll_lucid_evo_prepare(hw, true);
2333  }
2334  
alpha_pll_lucid_evo_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)2335  static unsigned long alpha_pll_lucid_evo_recalc_rate(struct clk_hw *hw,
2336  						     unsigned long parent_rate)
2337  {
2338  	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2339  	struct regmap *regmap = pll->clkr.regmap;
2340  	u32 l, frac;
2341  
2342  	regmap_read(regmap, PLL_L_VAL(pll), &l);
2343  	l &= LUCID_EVO_PLL_L_VAL_MASK;
2344  	regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac);
2345  
2346  	return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll));
2347  }
2348  
clk_lucid_evo_pll_postdiv_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)2349  static int clk_lucid_evo_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
2350  					      unsigned long parent_rate)
2351  {
2352  	return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_EVO_ENABLE_VOTE_RUN);
2353  }
2354  
2355  const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops = {
2356  	.enable = alpha_pll_lucid_evo_enable,
2357  	.disable = alpha_pll_lucid_evo_disable,
2358  	.is_enabled = clk_trion_pll_is_enabled,
2359  	.recalc_rate = alpha_pll_lucid_evo_recalc_rate,
2360  	.round_rate = clk_alpha_pll_round_rate,
2361  };
2362  EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_evo_ops);
2363  
2364  const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops = {
2365  	.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
2366  	.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
2367  	.set_rate = clk_lucid_evo_pll_postdiv_set_rate,
2368  };
2369  EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_evo_ops);
2370  
2371  const struct clk_ops clk_alpha_pll_lucid_evo_ops = {
2372  	.prepare = alpha_pll_lucid_evo_prepare,
2373  	.enable = alpha_pll_lucid_evo_enable,
2374  	.disable = alpha_pll_lucid_evo_disable,
2375  	.is_enabled = clk_trion_pll_is_enabled,
2376  	.recalc_rate = alpha_pll_lucid_evo_recalc_rate,
2377  	.round_rate = clk_alpha_pll_round_rate,
2378  	.set_rate = alpha_pll_lucid_5lpe_set_rate,
2379  };
2380  EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_evo_ops);
2381  
2382  const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops = {
2383  	.prepare = alpha_pll_reset_lucid_evo_prepare,
2384  	.enable = alpha_pll_lucid_evo_enable,
2385  	.disable = alpha_pll_reset_lucid_evo_disable,
2386  	.is_enabled = clk_trion_pll_is_enabled,
2387  	.recalc_rate = alpha_pll_lucid_evo_recalc_rate,
2388  	.round_rate = clk_alpha_pll_round_rate,
2389  	.set_rate = alpha_pll_lucid_5lpe_set_rate,
2390  };
2391  EXPORT_SYMBOL_GPL(clk_alpha_pll_reset_lucid_evo_ops);
2392  
clk_rivian_evo_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)2393  void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2394  				  const struct alpha_pll_config *config)
2395  {
2396  	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2397  	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
2398  	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
2399  	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2400  	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2401  	clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
2402  	clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
2403  	clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
2404  
2405  	regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2406  
2407  	regmap_update_bits(regmap, PLL_MODE(pll),
2408  			   PLL_RESET_N | PLL_BYPASSNL | PLL_OUTCTRL,
2409  			   PLL_RESET_N | PLL_BYPASSNL);
2410  }
2411  EXPORT_SYMBOL_GPL(clk_rivian_evo_pll_configure);
2412  
clk_rivian_evo_pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)2413  static unsigned long clk_rivian_evo_pll_recalc_rate(struct clk_hw *hw,
2414  						    unsigned long parent_rate)
2415  {
2416  	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2417  	u32 l;
2418  
2419  	regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
2420  
2421  	return parent_rate * l;
2422  }
2423  
clk_rivian_evo_pll_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)2424  static long clk_rivian_evo_pll_round_rate(struct clk_hw *hw, unsigned long rate,
2425  					  unsigned long *prate)
2426  {
2427  	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2428  	unsigned long min_freq, max_freq;
2429  	u32 l;
2430  	u64 a;
2431  
2432  	rate = alpha_pll_round_rate(rate, *prate, &l, &a, 0);
2433  	if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
2434  		return rate;
2435  
2436  	min_freq = pll->vco_table[0].min_freq;
2437  	max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
2438  
2439  	return clamp(rate, min_freq, max_freq);
2440  }
2441  
2442  const struct clk_ops clk_alpha_pll_rivian_evo_ops = {
2443  	.enable = alpha_pll_lucid_5lpe_enable,
2444  	.disable = alpha_pll_lucid_5lpe_disable,
2445  	.is_enabled = clk_trion_pll_is_enabled,
2446  	.recalc_rate = clk_rivian_evo_pll_recalc_rate,
2447  	.round_rate = clk_rivian_evo_pll_round_rate,
2448  };
2449  EXPORT_SYMBOL_GPL(clk_alpha_pll_rivian_evo_ops);
2450  
clk_stromer_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)2451  void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2452  			       const struct alpha_pll_config *config)
2453  {
2454  	u32 val, val_u, mask, mask_u;
2455  
2456  	regmap_write(regmap, PLL_L_VAL(pll), config->l);
2457  	regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
2458  	regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2459  
2460  	if (pll_has_64bit_config(pll))
2461  		regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
2462  			     config->config_ctl_hi_val);
2463  
2464  	if (pll_alpha_width(pll) > 32)
2465  		regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi);
2466  
2467  	val = config->main_output_mask;
2468  	val |= config->aux_output_mask;
2469  	val |= config->aux2_output_mask;
2470  	val |= config->early_output_mask;
2471  	val |= config->pre_div_val;
2472  	val |= config->post_div_val;
2473  	val |= config->vco_val;
2474  	val |= config->alpha_en_mask;
2475  	val |= config->alpha_mode_mask;
2476  
2477  	mask = config->main_output_mask;
2478  	mask |= config->aux_output_mask;
2479  	mask |= config->aux2_output_mask;
2480  	mask |= config->early_output_mask;
2481  	mask |= config->pre_div_mask;
2482  	mask |= config->post_div_mask;
2483  	mask |= config->vco_mask;
2484  	mask |= config->alpha_en_mask;
2485  	mask |= config->alpha_mode_mask;
2486  
2487  	regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
2488  
2489  	/* Stromer APSS PLL does not enable LOCK_DET by default, so enable it */
2490  	val_u = config->status_val << ALPHA_PLL_STATUS_REG_SHIFT;
2491  	val_u |= config->lock_det;
2492  
2493  	mask_u = config->status_mask;
2494  	mask_u |= config->lock_det;
2495  
2496  	regmap_update_bits(regmap, PLL_USER_CTL_U(pll), mask_u, val_u);
2497  	regmap_write(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2498  	regmap_write(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2499  
2500  	if (pll->flags & SUPPORTS_FSM_MODE)
2501  		qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
2502  }
2503  EXPORT_SYMBOL_GPL(clk_stromer_pll_configure);
2504  
clk_alpha_pll_stromer_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)2505  static int clk_alpha_pll_stromer_determine_rate(struct clk_hw *hw,
2506  						struct clk_rate_request *req)
2507  {
2508  	u32 l;
2509  	u64 a;
2510  
2511  	req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate,
2512  					 &l, &a, ALPHA_REG_BITWIDTH);
2513  
2514  	return 0;
2515  }
2516  
clk_alpha_pll_stromer_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)2517  static int clk_alpha_pll_stromer_set_rate(struct clk_hw *hw, unsigned long rate,
2518  					  unsigned long prate)
2519  {
2520  	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2521  	int ret;
2522  	u32 l;
2523  	u64 a;
2524  
2525  	rate = alpha_pll_round_rate(rate, prate, &l, &a, ALPHA_REG_BITWIDTH);
2526  
2527  	regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
2528  
2529  	a <<= ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH;
2530  	regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
2531  	regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
2532  		     a >> ALPHA_BITWIDTH);
2533  
2534  	regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
2535  			   PLL_ALPHA_EN, PLL_ALPHA_EN);
2536  
2537  	if (!clk_hw_is_enabled(hw))
2538  		return 0;
2539  
2540  	/*
2541  	 * Stromer PLL supports Dynamic programming.
2542  	 * It allows the PLL frequency to be changed on-the-fly without first
2543  	 * execution of a shutdown procedure followed by a bring up procedure.
2544  	 */
2545  	regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE,
2546  			   PLL_UPDATE);
2547  
2548  	ret = wait_for_pll_update(pll);
2549  	if (ret)
2550  		return ret;
2551  
2552  	return wait_for_pll_enable_lock(pll);
2553  }
2554  
2555  const struct clk_ops clk_alpha_pll_stromer_ops = {
2556  	.enable = clk_alpha_pll_enable,
2557  	.disable = clk_alpha_pll_disable,
2558  	.is_enabled = clk_alpha_pll_is_enabled,
2559  	.recalc_rate = clk_alpha_pll_recalc_rate,
2560  	.determine_rate = clk_alpha_pll_stromer_determine_rate,
2561  	.set_rate = clk_alpha_pll_stromer_set_rate,
2562  };
2563  EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_ops);
2564  
clk_alpha_pll_stromer_plus_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)2565  static int clk_alpha_pll_stromer_plus_set_rate(struct clk_hw *hw,
2566  					       unsigned long rate,
2567  					       unsigned long prate)
2568  {
2569  	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2570  	u32 l, alpha_width = pll_alpha_width(pll);
2571  	int ret, pll_mode;
2572  	u64 a;
2573  
2574  	rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
2575  
2576  	ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &pll_mode);
2577  	if (ret)
2578  		return ret;
2579  
2580  	regmap_write(pll->clkr.regmap, PLL_MODE(pll), 0);
2581  
2582  	/* Delay of 2 output clock ticks required until output is disabled */
2583  	udelay(1);
2584  
2585  	regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
2586  
2587  	if (alpha_width > ALPHA_BITWIDTH)
2588  		a <<= alpha_width - ALPHA_BITWIDTH;
2589  
2590  	regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
2591  	regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
2592  					a >> ALPHA_BITWIDTH);
2593  
2594  	regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
2595  			   PLL_ALPHA_EN, PLL_ALPHA_EN);
2596  
2597  	regmap_write(pll->clkr.regmap, PLL_MODE(pll), PLL_BYPASSNL);
2598  
2599  	/* Wait five micro seconds or more */
2600  	udelay(5);
2601  	regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N,
2602  			   PLL_RESET_N);
2603  
2604  	/* The lock time should be less than 50 micro seconds worst case */
2605  	usleep_range(50, 60);
2606  
2607  	ret = wait_for_pll_enable_lock(pll);
2608  	if (ret) {
2609  		pr_err("Wait for PLL enable lock failed [%s] %d\n",
2610  		       clk_hw_get_name(hw), ret);
2611  		return ret;
2612  	}
2613  
2614  	if (pll_mode & PLL_OUTCTRL)
2615  		regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL,
2616  				   PLL_OUTCTRL);
2617  
2618  	return 0;
2619  }
2620  
2621  const struct clk_ops clk_alpha_pll_stromer_plus_ops = {
2622  	.prepare = clk_alpha_pll_enable,
2623  	.unprepare = clk_alpha_pll_disable,
2624  	.is_enabled = clk_alpha_pll_is_enabled,
2625  	.recalc_rate = clk_alpha_pll_recalc_rate,
2626  	.determine_rate = clk_alpha_pll_stromer_determine_rate,
2627  	.set_rate = clk_alpha_pll_stromer_plus_set_rate,
2628  };
2629  EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_plus_ops);
2630