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Searched refs:PLLREFE_BASE_DIVN (Results 1 – 1 of 1) sorted by relevance

/openbmc/u-boot/arch/arm/mach-tegra/tegra210/
H A Dclock.c1076 #define PLLREFE_BASE_DIVN(n) (((n) & 0xff) << 8) macro
1098 PLLREFE_BASE_DIVN(0x41) | in tegra_pllref_enable()