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Searched refs:PLLCTL_PLLEN (Results 1 – 7 of 7) sorted by relevance

/openbmc/u-boot/arch/arm/mach-davinci/
H A Ddm365_lowlevel.c43 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN); in dm365_pll1_init()
97 setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN); in dm365_pll1_init()
125 clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN); in dm365_pll2_init()
174 setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN); in dm365_pll2_init()
H A Dda850_lowlevel.c51 clrbits_le32(&reg->pllctl, PLLCTL_PLLEN); in da850_pll_init()
146 setbits_le32(&reg->pllctl, PLLCTL_PLLEN); in da850_pll_init()
/openbmc/linux/arch/arm/mach-davinci/
H A Dpm.c51 val &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN); in davinci_pm_suspend()
97 val |= PLLCTL_PLLEN; in davinci_pm_suspend()
H A Dclock.h14 #define PLLCTL_PLLEN BIT(0) macro
H A Dsleep.S80 bic ip, ip, #PLLCTL_PLLEN
135 orr ip, ip, #PLLCTL_PLLEN
/openbmc/u-boot/arch/arm/mach-davinci/include/mach/
H A Dpll_defs.h46 #define PLLCTL_PLLEN (1 << 0) macro
/openbmc/linux/drivers/clk/davinci/
H A Dpll.c61 #define PLLCTL_PLLEN BIT(0) macro
318 ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN); in davinci_pllen_rate_change()
336 ctrl |= PLLCTL_PLLEN; in davinci_pllen_rate_change()