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Searched refs:PLLCTL (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/arch/arm/mach-davinci/
H A Dpm.c50 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
52 __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
57 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
59 __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
74 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
76 __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
79 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
81 __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
87 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
89 __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
[all …]
H A Dsleep.S78 ldr ip, [r3, #PLLCTL]
81 str ip, [r3, #PLLCTL]
89 ldr ip, [r3, #PLLCTL]
91 str ip, [r3, #PLLCTL]
109 ldr ip, [r3, #PLLCTL]
111 str ip, [r3, #PLLCTL]
114 ldr ip, [r3, #PLLCTL]
116 str ip, [r3, #PLLCTL]
123 ldr ip, [r3, #PLLCTL]
125 str ip, [r3, #PLLCTL]
[all …]
H A Dclock.h13 #define PLLCTL 0x100 macro
/openbmc/linux/drivers/clk/davinci/
H A Dpll.c36 #define PLLCTL 0x100 macro
314 ctrl = readl(pll->base + PLLCTL); in davinci_pllen_rate_change()
319 writel(ctrl, pll->base + PLLCTL); in davinci_pllen_rate_change()
325 writel(ctrl, pll->base + PLLCTL); in davinci_pllen_rate_change()
331 writel(ctrl, pll->base + PLLCTL); in davinci_pllen_rate_change()
337 writel(ctrl, pll->base + PLLCTL); in davinci_pllen_rate_change()
951 DEBUG_REG(PLLCTL),
/openbmc/u-boot/arch/arm/mach-davinci/
H A DKconfig70 int "PLLCTL Clock Mode"
73 Set PLLCTL Clock Mode bit as External Clock or On Chip oscillator
/openbmc/linux/sound/pci/ctxfi/
H A Dct20k1reg.h612 #define PLLCTL 0x1C6060 macro
H A Dcthw20k1.c1314 if (hw_read_20kx(hw, PLLCTL) == pllctl) in hw_pll_init()
1317 hw_write_20kx(hw, PLLCTL, pllctl); in hw_pll_init()
1959 data = hw_read_20kx(hw, PLLCTL); in hw_card_stop()
1960 hw_write_20kx(hw, PLLCTL, (data & (~(0x0F<<12)))); in hw_card_stop()