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Searched refs:PLL4 (Results 1 – 21 of 21) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,gcc-ipq8064.yaml34 - description: PLL4 from LCC
64 clocks = <&pxo_board>, <&cxo_board>, <&lcc PLL4>;
/openbmc/linux/include/dt-bindings/clock/
H A Dqcom,lcc-ipq806x.h9 #define PLL4 0 macro
H A Dqcom,lcc-msm8960.h9 #define PLL4 0 macro
H A Dstm32mp13-clks.h22 #define PLL4 9 macro
H A Dstm32mp1-clks.h186 #define PLL4 179 macro
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dti,j721e-cpb-audio.yaml19 clock for AUDIO_REFCLK2 needs to be changed between PLL4 (for 48KHz) and
25 PLL4 ---> PLL4_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
34 PLL4 ---> PLL4_HSDIV0 ---> MCASP0_AUXCLK ---> McASP0.auxclk
H A Dti,j721e-cpb-ivi-audio.yaml24 for AUDIO_REFCLK0 needs to be changed between PLL4 (for 48KHz) and PLL15 (for
28 Note: the same PLL4 and PLL15 is used by the audio support on the CPB!
31 PLL4 ---> PLL4_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
/openbmc/linux/arch/arm/boot/dts/st/
H A Dstm32mp157c-odyssey.dts41 assigned-clock-rates = <125000000>; /* Clock PLL4 to 750Mhz in ATF/U-Boot */
H A Dstm32mp15xc-lxa-tac.dtsi230 assigned-clock-rates = <125000000>; /* Clock PLL4 to 750Mhz in ATF */
/openbmc/u-boot/include/dt-bindings/clock/
H A Dstm32mp1-clks.h186 #define PLL4 179 macro
/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Dst,stm32mp1.txt25 MPU AXI MCU PLL12 PLL3 PLL4 RTC MCO1 MCO2
52 PLL children node for PLL1 to PLL4 : (see ref manual for details)
/openbmc/linux/drivers/clk/qcom/
H A Dlcc-ipq806x.c401 [PLL4] = &pll4.clkr,
H A Dlcc-msm8960.c397 [PLL4] = &pll4.clkr,
/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dqcom-msm8960.dtsi137 <&lcc PLL4>;
H A Dqcom-mdm9615.dtsi109 <&lcc PLL4>;
H A Dqcom-ipq8064.dtsi517 clocks = <&pxo_board>, <&cxo_board>, <&lcc PLL4>;
H A Dqcom-apq8064.dtsi809 <&lcc PLL4>;
/openbmc/linux/drivers/net/wireless/ath/ath9k/
H A Dreg.h1377 #define PLL4 0x1618c macro
H A Dhw.c744 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { in ar9003_get_pll_sqsum_dvc()
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-am65-main.dtsi1031 * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via
/openbmc/linux/drivers/clk/
H A Dclk-stm32mp1.c1776 PLL(PLL4, "pll4", ref4_parents, 0, RCC_PLL4CR, RCC_RCK4SELR),