| /openbmc/qemu/target/arm/ |
| H A D | cortex-regs.c | 32 .access = PL1_RW, .readfn = l2ctlr_read,
36 .access = PL1_RW, .readfn = l2ctlr_read,
40 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
43 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
46 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
49 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
52 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
55 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
58 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
61 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
[all …]
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| H A D | debug_helper.c | 962 .access = PL1_RW, .accessfn = access_tda,
983 .access = PL1_RW, .accessfn = access_tdcc,
987 .access = PL1_RW, .accessfn = access_tdcc,
1001 .access = PL1_RW, .accessfn = access_tda,
1029 .access = PL1_RW, .accessfn = access_tdosa,
1039 .access = PL1_RW, .accessfn = access_tda,
1048 .access = PL1_RW, .accessfn = access_tdcc,
1058 .access = PL1_RW, .accessfn = access_tda,
1063 .access = PL1_RW, .accessfn = access_tda,
1240 .access = PL1_RW, in define_debug_regs()
[all...] |
| H A D | helper.c | 297 * We assume that the .access field is set to PL1_RW.
635 .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
640 .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
652 .access = PL1_RW, .accessfn = access_tvm_trvm,
660 .access = PL1_RW, .accessfn = access_tvm_trvm,
674 .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0,
683 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
685 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
687 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
689 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
[all...] |
| H A D | cpregs.h | 304 PL1_RW = PL1_R | PL1_W, enumerator
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| /openbmc/qemu/target/arm/tcg/ |
| H A D | cpu32.c | 198 .access = PL1_RW, in arm1026_initfn()
338 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
340 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
389 .access = PL1_RW, .resetvalue = 0,
392 .access = PL1_RW, .resetvalue = 0,
395 .access = PL1_RW, .resetvalue = 0,
398 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
405 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
407 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
409 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
[all …]
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| H A D | cpu64.c | 482 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
499 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
503 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
507 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
518 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010,
534 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
538 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
542 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
546 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
558 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
[all …]
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| /openbmc/qemu/hw/intc/ |
| H A D | arm_gicv3_cpuif.c | 2436 .access = PL1_RW, .accessfn = gicv3_irqfiq_access, in icc_reset()
2466 .access = PL1_RW, .accessfn = gicv3_fiq_access,
2473 .access = PL1_RW, .accessfn = gicv3_fiq_access,
2481 .access = PL1_RW, .accessfn = gicv3_irq_access,
2555 .access = PL1_RW, .accessfn = gicv3_irq_access,
2563 .access = PL1_RW, .accessfn = gicv3_irqfiq_access,
2570 .access = PL1_RW,
2581 .access = PL1_RW, .accessfn = gicv3_fiq_access,
2590 .access = PL1_RW, .accessfn = gicv3_irq_access,
2633 .access = PL1_RW,
[all...] |
| H A D | arm_gicv3_kvm.c | 740 .access = PL1_RW,
|