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Searched refs:PIPR (Results 1 – 5 of 5) sorted by relevance

/openbmc/u-boot/drivers/net/
H A Dsh_eth.h140 PIPR, enumerator
206 [PIPR] = 0x052c,
H A Dsh_eth.c399 sh_eth_write(port_info, 0, PIPR); in sh_eth_mac_regs_config()
/openbmc/qemu/docs/specs/
H A Dppc-xive.rst137 - Interrupt Priority Register (PIPR)
162 Interrupt Priority Register (PIPR) is also updated using the IPB. This
166 The PIPR is then compared to the Current Processor Priority
H A Dppc-spapr-xive.rst220 CPU[0000]: QW NSR CPPR IPB LSMFB ACK# INC AGE PIPR W2
/openbmc/qemu/hw/intc/
H A Dtrace-events277 … uint8_t pipr, uint8_t cppr, uint8_t nsr) "target=%d ring=0x%x IPB=0x%02x PIPR=0x%02x CPPR=0x%02x …
278 … uint8_t pipr, uint8_t cppr, uint8_t nsr) "target=%d ring=0x%x IPB=0x%02x PIPR=0x%02x CPPR=0x%02x …
279 … uint8_t pipr, uint8_t cppr, uint8_t nsr) "target=%d ring=0x%x IPB=0x%02x PIPR=0x%02x new CPPR=0x%…