Home
last modified time | relevance | path

Searched refs:PIC (Results 1 – 25 of 91) sorted by relevance

1234

/openbmc/openbmc/meta-openembedded/meta-oe/recipes-networking/cyrus-sasl/cyrus-sasl/
H A Ddebian_patches_0014_avoid_pic_overwrite.diff6 Description: This patch makes sure the non-PIC version of libsasldb.a, which
7 is created out of non-PIC objects, is not going to overwrite the PIC version,
8 which is created out of PIC objects. The PIC version is placed in .libs, and
9 the non-PIC version in the current directory. This ensures that both non-PIC
10 and PIC versions are available in the correct locations.
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dopen-pic.txt1 * Open PIC Binding
4 representation of an Open PIC compliant interrupt controller. This binding is
5 based on the binding defined for Open PIC in [1] and is a superset of that
13 - compatible: Specifies the compatibility list for the PIC. The type
20 as an Open PIC. No property value shall be defined.
31 - pic-no-reset: The presence of this property indicates that the PIC
55 * An Open PIC interrupt controller
62 // this Open PIC node do not need a parent address specifier.
71 // Compatible with Open PIC.
74 // The PIC shall not be reset.
[all …]
H A Dmarvell,armada-8k-pic.txt1 Marvell Armada 7K/8K PIC Interrupt controller
4 This is the Device Tree binding for the PIC, a secondary interrupt
13 - reg: the register area for the PIC interrupt controller
H A Dintel,ce4100-lapic.yaml46 PIC Mode - Legacy external 8259 compliant PIC interrupt controller.
50 For OF based systems, it is by default set to PIC mode.
H A Dloongson,pch-pic.yaml7 title: Loongson PCH PIC Controller
27 to PCH PIC.
H A Dcdns,xtensa-mx.txt6 Remaining properties have exact same meaning as in Xtensa PIC
H A Dgoogle,goldfish-pic.txt1 Android Goldfish PIC
/openbmc/linux/Documentation/translations/zh_CN/arch/loongarch/
H A Dirq-chip-model.rst15 HTVECINTC(Hyper-Transport Vector Interrupt Controller)、PCH-PIC(LS7A芯片组的主中
19 全局中断控制器(每个芯片一个,所有核共享),而PCH-PIC/PCH-LPC/PCH-MSI是CPU外部的中
27 CPU串口(UARTs)中断发送到LIOINTC,而其他所有设备的中断则分别发送到所连接的PCH-PIC/
46 | PCH-PIC | | PCH-MSI |
63 CPU串口(UARTs)中断发送到LIOINTC,而其他所有设备的中断则分别发送到所连接的PCH-PIC/
77 | PCH-PIC | | PCH-MSI |
117 PCH-PIC::
156 - PCH-PIC/PCH-MSI:即《龙芯7A1000桥片用户手册》第5章所描述的“中断控制器”;
/openbmc/linux/arch/powerpc/boot/dts/
H A Dep8248e.dts72 interrupt-parent = <&PIC>;
77 interrupt-parent = <&PIC>;
135 interrupt-parent = <&PIC>;
148 interrupt-parent = <&PIC>;
161 interrupt-parent = <&PIC>;
174 interrupt-parent = <&PIC>;
186 interrupt-parent = <&PIC>;
192 PIC: interrupt-controller@10c00 { label
H A Dmgcoge.dts140 interrupt-parent = <&PIC>;
153 interrupt-parent = <&PIC>;
164 interrupt-parent = <&PIC>;
194 interrupt-parent = <&PIC>;
207 interrupt-parent = <&PIC>;
218 interrupt-parent = <&PIC>;
226 interrupt-parent = <&PIC>;
246 PIC: interrupt-controller@10c00 { label
H A Dmpc885ads.dts32 interrupt-parent = <&PIC>;
103 interrupt-parent = <&PIC>;
115 interrupt-parent = <&PIC>;
120 PIC: interrupt-controller@0 { label
134 interrupt-parent = <&PIC>;
171 interrupt-parent = <&PIC>;
228 interrupt-parent = <&PIC>;
H A Dtqm8xx.dts39 interrupt-parent = <&PIC>;
73 interrupt-parent = <&PIC>;
85 interrupt-parent = <&PIC>;
115 interrupt-parent = <&PIC>;
120 PIC: pic@0 { label
161 interrupt-parent = <&PIC>;
H A Dep88xc.dts32 interrupt-parent = <&PIC>;
98 interrupt-parent = <&PIC>;
110 interrupt-parent = <&PIC>;
115 PIC: interrupt-controller@0 { label
129 interrupt-parent = <&PIC>;
165 interrupt-parent = <&PIC>;
H A Dadder875-redboot.dts37 interrupt-parent = <&PIC>;
100 interrupt-parent = <&PIC>;
112 interrupt-parent = <&PIC>;
117 PIC: interrupt-controller@0 { label
156 interrupt-parent = <&PIC>;
H A Dadder875-uboot.dts37 interrupt-parent = <&PIC>;
99 interrupt-parent = <&PIC>;
111 interrupt-parent = <&PIC>;
116 PIC: interrupt-controller@0 { label
155 interrupt-parent = <&PIC>;
H A Dmpc866ads.dts32 interrupt-parent = <&PIC>;
83 interrupt-parent = <&PIC>;
88 PIC: pic@0 { label
129 interrupt-parent = <&PIC>;
H A Dgamecube.dts50 interrupt-parent = <&PIC>;
62 PIC: pic { label
/openbmc/linux/Documentation/arch/loongarch/
H A Dirq-chip-model.rst11 PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
15 controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e.,
24 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go
43 | PCH-PIC | | PCH-MSI |
61 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to
75 | PCH-PIC | | PCH-MSI |
115 PCH-PIC::
157 - PCH-PIC/PCH-MSI is "Interrupt Controller" described in Section 5 of
/openbmc/openbmc/poky/meta/recipes-extended/zip/zip-3.0/
H A D0002-configure-support-PIC-code-build.patch4 Subject: [PATCH 2/2] configure: support PIC code build
26 + # disable match.S for PIC code
/openbmc/openbmc/poky/meta/recipes-devtools/qemu/qemu/
H A D0003-apic-fixup-fallthrough-to-PIC.patch4 Subject: [PATCH 03/12] apic: fixup fallthrough to PIC
6 Commit 0e21e12bb311c4c1095d0269dc2ef81196ccb60a [Don't route PIC
/openbmc/qemu/tests/tcg/mips/
H A DMakefile.target17 hello-mips: CFLAGS+=-mno-abicalls -fno-PIC -fno-stack-protector -mabi=32
/openbmc/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm/
H A Dusb.txt13 interrupt-parent = <&PIC>;
/openbmc/qemu/docs/system/arm/
H A Dmainstone.rst13 - PIC
/openbmc/qemu/docs/system/openrisc/
H A Dcpu-features.rst10 - Programmable Interrupt Controller (PIC)
/openbmc/openbmc/meta-openembedded/meta-multimedia/recipes-multimedia/tinyalsa/
H A Dtinyalsa_2.0.0.bb18 # tinyalsa is built as a static library. Enable PIC to avoid relocation

1234