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Searched refs:PHY_REG_CONTROL_ANRESTART (Results 1 – 1 of 1) sorted by relevance

/openbmc/qemu/hw/net/
H A Dcadence_gem.c384 #define PHY_REG_CONTROL_ANRESTART 0x0200 macro
1510 val &= ~(PHY_REG_CONTROL_ANEG | PHY_REG_CONTROL_ANRESTART); in gem_phy_write()