Searched refs:PHY_AR8031_SERDES_TX_CLK_DLY (Results 1 – 1 of 1) sorted by relevance
71 #define PHY_AR8031_SERDES_TX_CLK_DLY 0x0100 /* TX clock delay of 2.0ns */ macro276 mii_reg |= PHY_AR8031_SERDES_TX_CLK_DLY; in pch_gbe_phy_tx_clk_delay()