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Searched refs:PHYS_SDRAM_0_SIZE (Results 1 – 11 of 11) sorted by relevance

/openbmc/u-boot/include/configs/
H A Dadp-ag101p.h176 (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20))
195 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
198 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ macro
202 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ macro
205 #define PHYS_SDRAM_0_SIZE 0x08000000 /* 128 MB */ macro
H A Dax25-ae350.h50 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
51 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ macro
78 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)
H A Dadp-ae3xx.h98 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
100 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ macro
H A Dsunxi-common.h104 #define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */ macro
/openbmc/u-boot/board/AndesTech/adp-ag101p/
H A Dadp-ag101p.c40 unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE; in dram_init()
58 gd->bd->bi_dram[0].size = PHYS_SDRAM_0_SIZE; in dram_init_banksize()
/openbmc/u-boot/board/AndesTech/adp-ae3xx/
H A Dadp-ae3xx.c36 unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE; in dram_init()
51 gd->bd->bi_dram[0].size = PHYS_SDRAM_0_SIZE; in dram_init_banksize()
/openbmc/u-boot/board/AndesTech/ax25-ae350/
H A Dax25-ae350.c32 unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE; in dram_init()
49 gd->bd->bi_dram[0].size = PHYS_SDRAM_0_SIZE; in dram_init_banksize()
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun4i.c689 return get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE); in dramc_init_helper()
/openbmc/u-boot/arch/nds32/include/asm/
H A Dio.h43 if(paddr <PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE) in map_sysmem()
/openbmc/u-boot/arch/riscv/include/asm/
H A Dio.h23 if (paddr < PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE) in map_sysmem()
/openbmc/u-boot/board/sunxi/
H A Dboard.c321 PHYS_SDRAM_0_SIZE); in dram_init()