Searched refs:PHYS_SDRAM_0 (Results 1 – 9 of 9) sorted by relevance
48 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ macro50 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */53 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_077 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_078 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)
185 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ macro188 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ macro190 #define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */ macro195 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */210 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0227 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0228 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000)
95 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ macro98 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */103 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0115 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0116 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000)
103 #define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE macro
32 gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400; in board_init()39 unsigned long sdram_base = PHYS_SDRAM_0; in dram_init()57 gd->bd->bi_dram[0].start = PHYS_SDRAM_0; in dram_init_banksize()
29 gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400; in board_init()35 unsigned long sdram_base = PHYS_SDRAM_0; in dram_init()50 gd->bd->bi_dram[0].start = PHYS_SDRAM_0; in dram_init_banksize()
24 gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400; in board_init()31 unsigned long sdram_base = PHYS_SDRAM_0; in dram_init()48 gd->bd->bi_dram[0].start = PHYS_SDRAM_0; in dram_init_banksize()
220 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100); in board_init()320 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, in dram_init()
689 return get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE); in dramc_init_helper()