Searched refs:PHI (Results 1 – 3 of 3) sorted by relevance
215 XEON PHI specific considerations218 The XEON PHI processor family is affected by MSBDS which can be exploited219 cross Hyper-Threads when entering idle states. Some XEON PHI variants allow224 XEON PHI is not affected by the other MDS variants and MSBDS is mitigated225 before the CPU enters a idle state. As XEON PHI is not affected by L1TF236 exception is XEON PHI, see :ref:`xeon_phi`.
22 - The Intel XEON PHI family
22 #define PHI 0x9e3779b9UL macro25 ({ b ^= d; b ^= c; b ^= a; b ^= PHI ^ i; b = rol32(b, 11); k[j] = b; })