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Searched refs:PHASE (Results 1 – 16 of 16) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_clock_source.h60 SRII(PHASE, DP_DTO, 0),\
61 SRII(PHASE, DP_DTO, 1),\
62 SRII(PHASE, DP_DTO, 2),\
63 SRII(PHASE, DP_DTO, 3),\
64 SRII(PHASE, DP_DTO, 4),\
65 SRII(PHASE, DP_DTO, 5),\
81 SRII(PHASE, DP_DTO, 0),\
82 SRII(PHASE, DP_DTO, 1),\
90 SRII(PHASE, DP_DTO, 0),\
91 SRII(PHASE, DP_DTO, 1),\
[all …]
H A Ddce_clock_source.c978 REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor); in dcn31_program_pix_clk()
982 REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100); in dcn31_program_pix_clk()
1089 clock_hz = REG_READ(PHASE[inst]); in get_pixel_clk_frequency_100hz()
1199 REG_WRITE(PHASE[inst], pixel_clk); in dcn20_override_dp_pix_clk()
1229 REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor); in dcn3_program_pix_clk()
1233 REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100); in dcn3_program_pix_clk()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_dccg.h53 DCCG_SRII(PHASE, DTBCLK_DTO, 0),\
54 DCCG_SRII(PHASE, DTBCLK_DTO, 1),\
55 DCCG_SRII(PHASE, DTBCLK_DTO, 2),\
56 DCCG_SRII(PHASE, DTBCLK_DTO, 3),\
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn314/
H A Ddcn314_dccg.h60 DCCG_SRII(PHASE, DTBCLK_DTO, 0),\
61 DCCG_SRII(PHASE, DTBCLK_DTO, 1),\
62 DCCG_SRII(PHASE, DTBCLK_DTO, 2),\
63 DCCG_SRII(PHASE, DTBCLK_DTO, 3),\
/openbmc/linux/sound/firewire/
H A DKconfig121 * TerraTec PHASE 24 FW/PHASE X24 FW/PHASE 88 Rack FW
/openbmc/linux/drivers/gpu/drm/nouveau/dispnv50/
H A Dhead917d.c44 NVVAL(NV917D, HEAD_SET_DITHER_CONTROL, PHASE, 0)); in head917d_dither()
H A Dheadc37d.c100 NVVAL(NVC37D, HEAD_SET_DITHER_CONTROL, PHASE, 0)); in headc37d_dither()
H A Dhead507d.c62 NVVAL(NV507D, HEAD_SET_DITHER_CONTROL, PHASE, 0)); in head507d_dither()
H A Dhead907d.c91 NVVAL(NV907D, HEAD_SET_DITHER_CONTROL, PHASE, 0)); in head907d_dither()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_resource.h182 SRII_ARR_2(PHASE, DP_DTO, 0, index), \
183 SRII_ARR_2(PHASE, DP_DTO, 1, index), \
184 SRII_ARR_2(PHASE, DP_DTO, 2, index), \
185 SRII_ARR_2(PHASE, DP_DTO, 3, index), \
1298 DCCG_SRII(PHASE, DTBCLK_DTO, 0), DCCG_SRII(PHASE, DTBCLK_DTO, 1), \
1299 DCCG_SRII(PHASE, DTBCLK_DTO, 2), DCCG_SRII(PHASE, DTBCLK_DTO, 3), \
/openbmc/linux/drivers/scsi/
H A DFlashPoint.c499 #define PHASE BIT(13) macro
1833 (PROG_HLT | RSEL | PHASE | BUS_FREE)); in FlashPoint_HandleInterrupt()
1869 (PHASE | IUNKWN | PROG_HLT)); in FlashPoint_HandleInterrupt()
2645 WRW_HARPOON((port + hp_intstat), PHASE); in FPT_sres()
2650 WRW_HARPOON((port + hp_intstat), PHASE); in FPT_sres()
2723 (PHASE | RESET)) in FPT_sres()
2815 WRW_HARPOON((port + hp_intstat), PHASE); in FPT_SendMsg()
2820 WRW_HARPOON((port + hp_intstat), PHASE); in FPT_SendMsg()
2823 (BUS_FREE | PHASE | XFER_CNT_0)); in FPT_SendMsg()
2839 (BUS_FREE | PHASE))) { in FPT_SendMsg()
[all …]
/openbmc/openbmc-tools/bi2cp/
H A Dbi2cp40 PHASE = (0x04, 1) variable in PMBusCommand
/openbmc/linux/Documentation/networking/
H A Dcan.rst1242 [ tq TQ prop-seg PROP_SEG phase-seg1 PHASE-SEG1
1243 phase-seg2 PHASE-SEG2 [ sjw SJW ] ]
1246 [ dtq TQ dprop-seg PROP_SEG dphase-seg1 PHASE-SEG1
1247 dphase-seg2 PHASE-SEG2 [ dsjw SJW ] ]
1266 PHASE-SEG1 := { 1..8 }
1267 PHASE-SEG2 := { 1..8 }
/openbmc/linux/Documentation/scsi/
H A DChangeLog.sym53c8xx341 to testing for a PHASE. SYMBIOS say this feature is working fine.
H A Dsym53c8xx_2.rst141 LOAD/STORE and handles PHASE MISMATCH from SCRIPTS for devices that
H A Dncr53c8xx.rst1233 have detected an expected disconnection (BUS FREE PHASE). For this process