1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * RISC-V processor specific defines
4 *
5 * Copyright (C) 2021 Western Digital Corporation or its affiliates.
6 */
7 #ifndef SELFTEST_KVM_PROCESSOR_H
8 #define SELFTEST_KVM_PROCESSOR_H
9
10 #include "kvm_util.h"
11 #include <linux/stringify.h>
12
__kvm_reg_id(uint64_t type,uint64_t idx,uint64_t size)13 static inline uint64_t __kvm_reg_id(uint64_t type, uint64_t idx,
14 uint64_t size)
15 {
16 return KVM_REG_RISCV | type | idx | size;
17 }
18
19 #if __riscv_xlen == 64
20 #define KVM_REG_SIZE_ULONG KVM_REG_SIZE_U64
21 #else
22 #define KVM_REG_SIZE_ULONG KVM_REG_SIZE_U32
23 #endif
24
25 #define RISCV_CONFIG_REG(name) __kvm_reg_id(KVM_REG_RISCV_CONFIG, \
26 KVM_REG_RISCV_CONFIG_REG(name), \
27 KVM_REG_SIZE_ULONG)
28
29 #define RISCV_CORE_REG(name) __kvm_reg_id(KVM_REG_RISCV_CORE, \
30 KVM_REG_RISCV_CORE_REG(name), \
31 KVM_REG_SIZE_ULONG)
32
33 #define RISCV_CSR_REG(name) __kvm_reg_id(KVM_REG_RISCV_CSR, \
34 KVM_REG_RISCV_CSR_REG(name), \
35 KVM_REG_SIZE_ULONG)
36
37 #define RISCV_TIMER_REG(name) __kvm_reg_id(KVM_REG_RISCV_TIMER, \
38 KVM_REG_RISCV_TIMER_REG(name), \
39 KVM_REG_SIZE_U64)
40
41 #define RISCV_ISA_EXT_REG(idx) __kvm_reg_id(KVM_REG_RISCV_ISA_EXT, \
42 idx, KVM_REG_SIZE_ULONG)
43
44 /* L3 index Bit[47:39] */
45 #define PGTBL_L3_INDEX_MASK 0x0000FF8000000000ULL
46 #define PGTBL_L3_INDEX_SHIFT 39
47 #define PGTBL_L3_BLOCK_SHIFT 39
48 #define PGTBL_L3_BLOCK_SIZE 0x0000008000000000ULL
49 #define PGTBL_L3_MAP_MASK (~(PGTBL_L3_BLOCK_SIZE - 1))
50 /* L2 index Bit[38:30] */
51 #define PGTBL_L2_INDEX_MASK 0x0000007FC0000000ULL
52 #define PGTBL_L2_INDEX_SHIFT 30
53 #define PGTBL_L2_BLOCK_SHIFT 30
54 #define PGTBL_L2_BLOCK_SIZE 0x0000000040000000ULL
55 #define PGTBL_L2_MAP_MASK (~(PGTBL_L2_BLOCK_SIZE - 1))
56 /* L1 index Bit[29:21] */
57 #define PGTBL_L1_INDEX_MASK 0x000000003FE00000ULL
58 #define PGTBL_L1_INDEX_SHIFT 21
59 #define PGTBL_L1_BLOCK_SHIFT 21
60 #define PGTBL_L1_BLOCK_SIZE 0x0000000000200000ULL
61 #define PGTBL_L1_MAP_MASK (~(PGTBL_L1_BLOCK_SIZE - 1))
62 /* L0 index Bit[20:12] */
63 #define PGTBL_L0_INDEX_MASK 0x00000000001FF000ULL
64 #define PGTBL_L0_INDEX_SHIFT 12
65 #define PGTBL_L0_BLOCK_SHIFT 12
66 #define PGTBL_L0_BLOCK_SIZE 0x0000000000001000ULL
67 #define PGTBL_L0_MAP_MASK (~(PGTBL_L0_BLOCK_SIZE - 1))
68
69 #define PGTBL_PTE_ADDR_MASK 0x003FFFFFFFFFFC00ULL
70 #define PGTBL_PTE_ADDR_SHIFT 10
71 #define PGTBL_PTE_RSW_MASK 0x0000000000000300ULL
72 #define PGTBL_PTE_RSW_SHIFT 8
73 #define PGTBL_PTE_DIRTY_MASK 0x0000000000000080ULL
74 #define PGTBL_PTE_DIRTY_SHIFT 7
75 #define PGTBL_PTE_ACCESSED_MASK 0x0000000000000040ULL
76 #define PGTBL_PTE_ACCESSED_SHIFT 6
77 #define PGTBL_PTE_GLOBAL_MASK 0x0000000000000020ULL
78 #define PGTBL_PTE_GLOBAL_SHIFT 5
79 #define PGTBL_PTE_USER_MASK 0x0000000000000010ULL
80 #define PGTBL_PTE_USER_SHIFT 4
81 #define PGTBL_PTE_EXECUTE_MASK 0x0000000000000008ULL
82 #define PGTBL_PTE_EXECUTE_SHIFT 3
83 #define PGTBL_PTE_WRITE_MASK 0x0000000000000004ULL
84 #define PGTBL_PTE_WRITE_SHIFT 2
85 #define PGTBL_PTE_READ_MASK 0x0000000000000002ULL
86 #define PGTBL_PTE_READ_SHIFT 1
87 #define PGTBL_PTE_PERM_MASK (PGTBL_PTE_ACCESSED_MASK | \
88 PGTBL_PTE_DIRTY_MASK | \
89 PGTBL_PTE_EXECUTE_MASK | \
90 PGTBL_PTE_WRITE_MASK | \
91 PGTBL_PTE_READ_MASK)
92 #define PGTBL_PTE_VALID_MASK 0x0000000000000001ULL
93 #define PGTBL_PTE_VALID_SHIFT 0
94
95 #define PGTBL_PAGE_SIZE PGTBL_L0_BLOCK_SIZE
96 #define PGTBL_PAGE_SIZE_SHIFT PGTBL_L0_BLOCK_SHIFT
97
98 #define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL)
99 #define SATP_MODE_39 _AC(0x8000000000000000, UL)
100 #define SATP_MODE_48 _AC(0x9000000000000000, UL)
101 #define SATP_ASID_BITS 16
102 #define SATP_ASID_SHIFT 44
103 #define SATP_ASID_MASK _AC(0xFFFF, UL)
104
105 #define SBI_EXT_EXPERIMENTAL_START 0x08000000
106 #define SBI_EXT_EXPERIMENTAL_END 0x08FFFFFF
107
108 #define KVM_RISCV_SELFTESTS_SBI_EXT SBI_EXT_EXPERIMENTAL_END
109 #define KVM_RISCV_SELFTESTS_SBI_UCALL 0
110 #define KVM_RISCV_SELFTESTS_SBI_UNEXP 1
111
112 struct sbiret {
113 long error;
114 long value;
115 };
116
117 struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
118 unsigned long arg1, unsigned long arg2,
119 unsigned long arg3, unsigned long arg4,
120 unsigned long arg5);
121
122 #endif /* SELFTEST_KVM_PROCESSOR_H */
123