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Searched refs:PFIFO (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/video/fbdev/nvidia/
H A Dnv_hw.c1475 NV_WR32(par->PFIFO, 0x0140 * 4, 0x00000000); in NVLoadStateExt()
1476 NV_WR32(par->PFIFO, 0x0141 * 4, 0x00000001); in NVLoadStateExt()
1477 NV_WR32(par->PFIFO, 0x0480 * 4, 0x00000000); in NVLoadStateExt()
1478 NV_WR32(par->PFIFO, 0x0494 * 4, 0x00000000); in NVLoadStateExt()
1483 NV_WR32(par->PFIFO, 0x0490 * 4, 0x00000000); in NVLoadStateExt()
1484 NV_WR32(par->PFIFO, 0x0491 * 4, 0x00000000); in NVLoadStateExt()
1489 NV_WR32(par->PFIFO, 0x0400 * 4, 0x00000000); in NVLoadStateExt()
1490 NV_WR32(par->PFIFO, 0x0414 * 4, 0x00000000); in NVLoadStateExt()
1491 NV_WR32(par->PFIFO, 0x0084 * 4, 0x03000100); in NVLoadStateExt()
1492 NV_WR32(par->PFIFO, 0x0085 * 4, 0x00000110); in NVLoadStateExt()
[all …]
H A Dnv_type.h160 volatile u32 __iomem *PFIFO; member
H A Dnv_setup.c299 par->PFIFO = par->REGS + (0x00002000 / 4); in NVCommonSetup()
/openbmc/linux/drivers/video/fbdev/riva/
H A Dnvreg.h105 #define PFIFO_Write(reg,value) DEVICE_WRITE(PFIFO,reg,value)
106 #define PFIFO_Read(reg) DEVICE_READ(PFIFO,reg)
107 #define PFIFO_Print(reg) DEVICE_PRINT(PFIFO,reg)
108 #define PFIFO_Def(mask,value) DEVICE_DEF(PFIFO,mask,value)
109 #define PFIFO_Val(mask,value) DEVICE_VALUE(PFIFO,mask,value)
110 #define PFIFO_Mask(mask) DEVICE_MASK(PFIFO,mask)
H A Dnv_driver.c322 par->riva.PFIFO = in riva_common_setup()
H A Driva_hw.h448 volatile U032 __iomem *PFIFO; member
H A Driva_hw.c1388 LOAD_FIXED_STATE(nv3,PFIFO); in LoadStateExt()
1428 LOAD_FIXED_STATE(nv4,PFIFO); in LoadStateExt()
1474 LOAD_FIXED_STATE(nv10,PFIFO); in LoadStateExt()
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/
H A Dg98.fuc0s164 // tell PFIFO we unloaded
175 // if bit 30 of next channel not set, probably PFIFO is just
193 // tell PFIFO we're done