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Searched refs:PER_M4X2 (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/include/asm/arch-omap3/
H A Dclocks_omap3.h34 #define PER_M4X2 2 /* 432MHz: CM_CLKSEL_DSS-dss1 */ macro
/openbmc/u-boot/arch/arm/mach-omap2/omap3/
H A Dclock.c257 clrsetbits_le32(&prcm_base->clksel_dss, 0x0000001F, (PER_M4X2 + 1)); in dpll4_init_34xx()
258 clrsetbits_le32(&prcm_base->clksel_dss, 0x0000001F, PER_M4X2); in dpll4_init_34xx()