Searched refs:PDAUDIOCF_CLKDIV0 (Results 1 – 2 of 2) sorted by relevance
37 #define PDAUDIOCF_CLKDIV0 (1<<4) /* choose 24.576Mhz clock divided by 1,2,3 or 4 */ macro
208 val &= ~(PDAUDIOCF_CLKDIV0 | PDAUDIOCF_CLKDIV1); /* use 24.576Mhz clock */ in snd_pdacf_ak4117_create()