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Searched refs:PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_3_0_sh_mask.h7554 #define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x0000007eL macro
H A Dbif_4_1_sh_mask.h2879 #define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e macro
H A Dbif_5_0_sh_mask.h10559 #define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e macro
H A Dbif_5_1_sh_mask.h3833 #define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_4_sh_mask.h42352 #define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK … macro
H A Dnbio_4_3_0_sh_mask.h31263 #define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK … macro
H A Dnbio_2_3_sh_mask.h53489 #define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK … macro
H A Dnbio_6_1_sh_mask.h37727 #define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK … macro