Searched refs:PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK (Results 1 – 15 of 15) sorted by relevance
509 link_width = (reg_data & PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK) in nbio_v2_3_apply_lc_spc_mode_wa()
73 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L macro2081 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK) in smu_v11_0_get_current_pcie_link_width_level()
79 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L macro2029 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK) in smu_v13_0_get_current_pcie_link_width_level()
85 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L macro
2239 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK) in vega12_get_current_pcie_link_width_level()
3330 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK) in vega20_get_current_pcie_link_width_level()
4664 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK) in vega10_get_current_pcie_link_width_level()
7107 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L macro
3253 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70 macro
11001 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70 macro
4207 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70 macro
42679 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK … macro
31571 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK … macro
53822 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK … macro
38039 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK … macro