1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2016 Google, Inc 4 */ 5 6 #ifndef __ASM_ARCH_PCH_H 7 #define __ASM_ARCH_PCH_H 8 9 /* CPU bus clock is fixed at 100MHz */ 10 #define CPU_BCLK 100 11 12 #define PMBASE 0x40 13 #define ACPI_CNTL 0x44 14 #define ACPI_EN (1 << 7) 15 16 #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ 17 #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ 18 #define GPIO_EN (1 << 4) 19 20 #define PCIEXBAR 0x60 21 22 #define PCH_DEV_LPC PCI_BDF(0, 0x1f, 0) 23 24 /* RCB registers */ 25 #define OIC 0x31fe /* 16bit */ 26 #define HPTC 0x3404 /* 32bit */ 27 #define FD 0x3418 /* 32bit */ 28 29 /* Function Disable 1 RCBA 0x3418 */ 30 #define PCH_DISABLE_ALWAYS (1 << 0) 31 32 /* PM registers */ 33 #define TCO1_CNT 0x60 34 #define TCO_TMR_HLT (1 << 11) 35 36 37 /* Device 0:0.0 PCI configuration space */ 38 39 #define EPBAR 0x40 40 #define MCHBAR 0x48 41 #define PCIEXBAR 0x60 42 #define DMIBAR 0x68 43 #define GGC 0x50 /* GMCH Graphics Control */ 44 #define DEVEN 0x54 /* Device Enable */ 45 #define DEVEN_D7EN (1 << 14) 46 #define DEVEN_D4EN (1 << 7) 47 #define DEVEN_D3EN (1 << 5) 48 #define DEVEN_D2EN (1 << 4) 49 #define DEVEN_D1F0EN (1 << 3) 50 #define DEVEN_D1F1EN (1 << 2) 51 #define DEVEN_D1F2EN (1 << 1) 52 #define DEVEN_D0EN (1 << 0) 53 #define DPR 0x5c 54 #define DPR_EPM (1 << 2) 55 #define DPR_PRS (1 << 1) 56 #define DPR_SIZE_MASK 0xff0 57 58 #define MCHBAR_PEI_VERSION 0x5034 59 #define BIOS_RESET_CPL 0x5da8 60 #define EDRAMBAR 0x5408 61 #define MCH_PAIR 0x5418 62 #define GDXCBAR 0x5420 63 64 #define PAM0 0x80 65 #define PAM1 0x81 66 #define PAM2 0x82 67 #define PAM3 0x83 68 #define PAM4 0x84 69 #define PAM5 0x85 70 #define PAM6 0x86 71 72 /* PCODE MMIO communications live in the MCHBAR. */ 73 #define BIOS_MAILBOX_INTERFACE 0x5da4 74 #define MAILBOX_RUN_BUSY (1 << 31) 75 #define MAILBOX_BIOS_CMD_READ_PCS 1 76 #define MAILBOX_BIOS_CMD_WRITE_PCS 2 77 #define MAILBOX_BIOS_CMD_READ_CALIBRATION 0x509 78 #define MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL 0x909 79 #define MAILBOX_BIOS_CMD_READ_PCH_POWER 0xa 80 #define MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT 0xb 81 #define MAILBOX_BIOS_CMD_READ_C9C10_VOLTAGE 0x26 82 #define MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE 0x27 83 /* Errors are returned back in bits 7:0. */ 84 #define MAILBOX_BIOS_ERROR_NONE 0 85 #define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1 86 #define MAILBOX_BIOS_ERROR_TIMEOUT 2 87 #define MAILBOX_BIOS_ERROR_ILLEGAL_DATA 3 88 #define MAILBOX_BIOS_ERROR_RESERVED 4 89 #define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5 90 #define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6 91 #define MAILBOX_BIOS_ERROR_VR_ERROR 7 92 /* Data is passed through bits 31:0 of the data register. */ 93 #define BIOS_MAILBOX_DATA 0x5da0 94 95 /* SATA IOBP Registers */ 96 #define SATA_IOBP_SP0_SECRT88 0xea002688 97 #define SATA_IOBP_SP1_SECRT88 0xea002488 98 99 #define SATA_SECRT88_VADJ_MASK 0xff 100 #define SATA_SECRT88_VADJ_SHIFT 16 101 102 #define SATA_IOBP_SP0DTLE_DATA 0xea002550 103 #define SATA_IOBP_SP0DTLE_EDGE 0xea002554 104 #define SATA_IOBP_SP1DTLE_DATA 0xea002750 105 #define SATA_IOBP_SP1DTLE_EDGE 0xea002754 106 107 #define SATA_DTLE_MASK 0xF 108 #define SATA_DTLE_DATA_SHIFT 24 109 #define SATA_DTLE_EDGE_SHIFT 16 110 111 /* Power Management */ 112 #define PCH_PCS 0x84 113 #define PCH_PCS_PS_D3HOT 3 114 115 #define GEN_PMCON_1 0xa0 116 #define SMI_LOCK (1 << 4) 117 #define GEN_PMCON_2 0xa2 118 #define SYSTEM_RESET_STS (1 << 4) 119 #define THERMTRIP_STS (1 << 3) 120 #define SYSPWR_FLR (1 << 1) 121 #define PWROK_FLR (1 << 0) 122 #define GEN_PMCON_3 0xa4 123 #define SUS_PWR_FLR (1 << 14) 124 #define GEN_RST_STS (1 << 9) 125 #define RTC_BATTERY_DEAD (1 << 2) 126 #define PWR_FLR (1 << 1) 127 #define SLEEP_AFTER_POWER_FAIL (1 << 0) 128 #define GEN_PMCON_LOCK 0xa6 129 #define SLP_STR_POL_LOCK (1 << 2) 130 #define ACPI_BASE_LOCK (1 << 1) 131 #define PMIR 0xac 132 #define PMIR_CF9LOCK (1 << 31) 133 #define PMIR_CF9GR (1 << 20) 134 135 /* Broadwell PCH (Wildcat Point) */ 136 #define PCH_WPT_HSW_U_SAMPLE 0x9cc1 137 #define PCH_WPT_BDW_U_SAMPLE 0x9cc2 138 #define PCH_WPT_BDW_U_PREMIUM 0x9cc3 139 #define PCH_WPT_BDW_U_BASE 0x9cc5 140 #define PCH_WPT_BDW_Y_SAMPLE 0x9cc6 141 #define PCH_WPT_BDW_Y_PREMIUM 0x9cc7 142 #define PCH_WPT_BDW_Y_BASE 0x9cc9 143 #define PCH_WPT_BDW_H 0x9ccb 144 145 #define SA_IGD_OPROM_VENDEV 0x80860406 146 147 /* Dynamically determine if the part is ULT */ 148 bool cpu_is_ult(void); 149 150 u32 pch_iobp_read(u32 address); 151 int pch_iobp_write(u32 address, u32 data); 152 int pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); 153 int pch_iobp_exec(u32 addr, u16 op_dcode, u8 route_id, u32 *data, u8 *resp); 154 155 #endif 156