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Searched refs:PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h6892 #define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L macro
H A Dgfx_7_2_sh_mask.h5795 #define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 macro
H A Dgfx_8_0_sh_mask.h6583 #define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 macro
H A Dgfx_8_1_sh_mask.h7117 #define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h21492 #define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK … macro
H A Dgc_9_2_1_sh_mask.h22752 #define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK … macro
H A Dgc_9_1_sh_mask.h22803 #define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK … macro
H A Dgc_9_4_3_sh_mask.h24947 #define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK … macro
H A Dgc_9_4_2_sh_mask.h16567 #define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK … macro
H A Dgc_11_0_0_sh_mask.h31650 #define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK … macro
H A Dgc_11_0_3_sh_mask.h34148 #define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK … macro
H A Dgc_10_1_0_sh_mask.h31397 #define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK … macro
H A Dgc_10_3_0_sh_mask.h29765 #define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK … macro