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Searched refs:PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK (Results 1 – 14 of 14) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v7_0.c2003 WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK); in gfx_v7_0_constants_init()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h6396 #define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x00000001L macro
H A Dgfx_7_2_sh_mask.h6547 #define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x1 macro
H A Dgfx_8_1_sh_mask.h7871 #define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x1 macro
H A Dgfx_8_0_sh_mask.h7335 #define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x1 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h1970 #define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK … macro
H A Dgc_9_1_sh_mask.h1828 #define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK … macro
H A Dgc_9_2_1_sh_mask.h1825 #define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK … macro
H A Dgc_9_4_3_sh_mask.h1929 #define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK … macro
H A Dgc_9_4_2_sh_mask.h15352 #define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK … macro
H A Dgc_11_0_0_sh_mask.h24115 #define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK … macro
H A Dgc_10_1_0_sh_mask.h7538 #define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK … macro
H A Dgc_11_0_3_sh_mask.h26461 #define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK … macro
H A Dgc_10_3_0_sh_mask.h7861 #define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK … macro