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Searched refs:PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT (Results 1 – 10 of 10) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_1_sh_mask.h7948 #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT 0x0 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h2048 #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT … macro
H A Dgc_9_1_sh_mask.h1904 #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h1919 #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT … macro
H A Dgc_9_4_3_sh_mask.h2023 #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT … macro
H A Dgc_9_4_2_sh_mask.h15444 #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT … macro
H A Dgc_11_0_0_sh_mask.h24329 #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h7626 #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h26681 #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h7947 #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT … macro