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Searched refs:PAD_CTL_DSE_3P3V_49OHM (Results 1 – 6 of 6) sorted by relevance

/openbmc/u-boot/board/freescale/mx7dsabresd/
H A Dmx7dsabresd.c28 #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
31 #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
34 #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
37 PAD_CTL_DSE_3P3V_49OHM)
39 #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
42 (PAD_CTL_HYS | PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST)
44 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
/openbmc/u-boot/board/toradex/colibri_imx7/
H A Dcolibri_imx7.c33 #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
36 #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
39 #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
42 PAD_CTL_DSE_3P3V_49OHM)
44 #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
46 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
/openbmc/u-boot/board/technexion/pico-imx7d/
H A Dpico-imx7d.c28 #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
34 #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
37 #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
44 PAD_CTL_DSE_3P3V_49OHM)
/openbmc/u-boot/board/compulab/cl-som-imx7/
H A Dmux.c41 #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
96 #define ENET_PAD_CTRL (PAD_CTL_PUS_PD100KOHM | PAD_CTL_DSE_3P3V_49OHM)
/openbmc/u-boot/board/warp7/
H A Dwarp7.c27 #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \
/openbmc/u-boot/arch/arm/include/asm/mach-imx/
H A Diomux-v3.h119 #define PAD_CTL_DSE_3P3V_49OHM (0x1<<0) macro