Home
last modified time | relevance | path

Searched refs:OTG_H_TIMING_DIV_MODE (Results 1 – 11 of 11) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn314/
H A Ddcn314_optc.c102 OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc314_set_odm_combine()
180 OTG_H_TIMING_DIV_MODE, h_div); in optc314_set_odm_bypass()
H A Ddcn314_optc.h248 SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_optc.c90 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc31_set_odm_combine()
228 OTG_H_TIMING_DIV_MODE, 0); in optc3_init_odm()
H A Ddcn31_optc.h251 SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_optc.c97 OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc32_set_odm_combine()
213 OTG_H_TIMING_DIV_MODE, h_div); in optc32_set_odm_bypass()
H A Ddcn32_optc.h176 SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_optc.c211 OTG_H_TIMING_DIV_MODE, h_div); in optc3_set_odm_bypass()
272 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc3_set_odm_combine()
H A Ddcn30_optc.h320 SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_optc.c314 if (optc1->tg_mask->OTG_H_TIMING_DIV_MODE != 0) { in optc1_program_timing()
319 OTG_H_TIMING_DIV_MODE, h_div); in optc1_program_timing()
H A Ddcn10_optc.h544 type OTG_H_TIMING_DIV_MODE;\
/openbmc/linux/drivers/gpu/drm/amd/include/
H A Dsoc21_enum.h4314 typedef enum OTG_H_TIMING_DIV_MODE { enum
4319 } OTG_H_TIMING_DIV_MODE; typedef