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Searched refs:OTG_CONTROL (Results 1 – 11 of 11) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_optc.c130 REG_UPDATE_2(OTG_CONTROL, in optc32_enable_crtc()
158 REG_UPDATE(OTG_CONTROL, in optc32_disable_crtc()
177 REG_UPDATE_2(OTG_CONTROL, OTG_DISABLE_POINT_CNTL, 0, OTG_MASTER_EN, 0); in optc32_phantom_crtc_post_enable()
194 REG_UPDATE(OTG_CONTROL, OTG_MASTER_EN, 0); in optc32_disable_phantom_otg()
H A Ddcn32_resource.h1049 SRI_ARR(OTG_CONTROL, OTG, inst), SRI_ARR(OTG_STEREO_CONTROL, OTG, inst), \
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn314/
H A Ddcn314_optc.c121 REG_UPDATE_2(OTG_CONTROL, in optc314_enable_crtc()
139 REG_UPDATE(OTG_CONTROL, in optc314_disable_crtc()
158 REG_UPDATE_2(OTG_CONTROL, OTG_DISABLE_POINT_CNTL, 0, OTG_MASTER_EN, 0); in optc314_phantom_crtc_post_enable()
H A Ddcn314_optc.h51 SRI(OTG_CONTROL, OTG, inst),\
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_optc.c69 REG_UPDATE_2(OTG_CONTROL, in optc2_enable_crtc()
284 REG_UPDATE(OTG_CONTROL, OTG_MASTER_EN, 0); in optc2_align_vblanks()
286 REG_WAIT(OTG_CONTROL, in optc2_align_vblanks()
343 REG_UPDATE(OTG_CONTROL, in optc2_align_vblanks()
360 REG_WAIT(OTG_CONTROL, in optc2_align_vblanks()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_optc.c112 REG_UPDATE_2(OTG_CONTROL, in optc31_enable_crtc()
129 REG_UPDATE(OTG_CONTROL, in optc31_disable_crtc()
148 REG_UPDATE_2(OTG_CONTROL, in optc31_immediate_disable_crtc()
H A Ddcn31_optc.h50 SRI(OTG_CONTROL, OTG, inst),\
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_optc.c277 REG_UPDATE_2(OTG_CONTROL, in optc1_program_timing()
539 REG_UPDATE_2(OTG_CONTROL, in optc1_enable_crtc()
557 REG_UPDATE_2(OTG_CONTROL, in optc1_disable_crtc()
1329 REG_GET(OTG_CONTROL, in optc1_read_otg_state()
1400 REG_GET(OTG_CONTROL, in optc1_get_otg_active_size()
1438 REG_GET(OTG_CONTROL, OTG_MASTER_EN, &otg_enabled); in optc1_is_tg_enabled()
H A Ddcn10_optc.h52 SRI(OTG_CONTROL, OTG, inst),\
124 uint32_t OTG_CONTROL; member
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_optc.c139 REG_UPDATE(OTG_CONTROL, OTG_OUT_MUX, dest); in optc3_set_out_mux()
H A Ddcn30_optc.h52 SRI(OTG_CONTROL, OTG, inst),\