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Searched refs:OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_1_sh_mask.h26209 #define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK … macro
H A Ddcn_3_2_1_sh_mask.h27534 #define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK … macro
H A Ddcn_3_1_2_sh_mask.h32490 #define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK … macro
H A Ddcn_3_1_6_sh_mask.h33256 #define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK … macro
H A Ddcn_3_0_2_sh_mask.h29557 #define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK … macro
H A Ddcn_3_1_4_sh_mask.h34377 #define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK … macro
H A Ddcn_3_0_0_sh_mask.h33085 #define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK … macro
H A Ddcn_3_2_0_sh_mask.h27531 #define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK … macro