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Searched refs:OTG3_OTG_CONTROL__OTG_OUT_MUX_MASK (Results 1 – 9 of 9) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_1_sh_mask.h25644 #define OTG3_OTG_CONTROL__OTG_OUT_MUX_MASK … macro
H A Ddcn_3_2_1_sh_mask.h26992 #define OTG3_OTG_CONTROL__OTG_OUT_MUX_MASK … macro
H A Ddcn_3_1_2_sh_mask.h31935 #define OTG3_OTG_CONTROL__OTG_OUT_MUX_MASK … macro
H A Ddcn_3_1_5_sh_mask.h29873 #define OTG3_OTG_CONTROL__OTG_OUT_MUX_MASK … macro
H A Ddcn_3_1_6_sh_mask.h32701 #define OTG3_OTG_CONTROL__OTG_OUT_MUX_MASK … macro
H A Ddcn_3_1_4_sh_mask.h33835 #define OTG3_OTG_CONTROL__OTG_OUT_MUX_MASK … macro
H A Ddcn_3_0_2_sh_mask.h28992 #define OTG3_OTG_CONTROL__OTG_OUT_MUX_MASK … macro
H A Ddcn_3_0_0_sh_mask.h32520 #define OTG3_OTG_CONTROL__OTG_OUT_MUX_MASK … macro
H A Ddcn_3_2_0_sh_mask.h26989 #define OTG3_OTG_CONTROL__OTG_OUT_MUX_MASK … macro