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Searched refs:OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_sh_mask.h15263 #define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT macro
H A Ddcn_3_0_3_sh_mask.h15413 #define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT macro
H A Ddcn_3_0_1_sh_mask.h24121 #define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT macro
H A Ddcn_2_1_0_sh_mask.h28563 #define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT macro
H A Ddcn_3_2_1_sh_mask.h25515 #define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT macro
H A Ddcn_1_0_sh_mask.h22670 #define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT macro
H A Ddcn_3_1_2_sh_mask.h30436 #define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT macro
H A Ddcn_3_1_6_sh_mask.h31202 #define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT macro
H A Ddcn_3_0_2_sh_mask.h27469 #define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT macro
H A Ddcn_3_1_4_sh_mask.h32358 #define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT macro
H A Ddcn_3_0_0_sh_mask.h30999 #define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT macro
H A Ddcn_2_0_0_sh_mask.h31908 #define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT macro
H A Ddcn_3_2_0_sh_mask.h25512 #define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT macro